MCP6V82 datasheet(6/48 Pages) MICROCHIP

6 / 48 page

MCP6V81/1U/2/4

DS20005419B-page 6

 2016 Microchip Technology Inc.

1.3

Timing Diagrams

FIGURE 1-1:

Amplifier Start-Up.

FIGURE 1-2:

Offset Correction Settling

Time.

FIGURE 1-3:

Output Overdrive Recovery.

1.4

Test Circuits

The circuits used for most DC and AC tests are shown

in Figures 1-4 and 1-5. Lay the bypass capacitors out

as discussed in Section 4.3.10 “Supply Bypassing

and Filtering”

. RN is equal to the parallel combination

of RF and RG to minimize bias current effects.

FIGURE 1-4:

AC and DC Test Circuit for

Most Non-Inverting Gain Conditions.

FIGURE 1-5:

AC and DC Test Circuit for

Most Inverting Gain Conditions.

The circuit in Figure 1-6 tests the input’s dynamic

behavior (i.e., IMD, tSTR, tSTL and tODR). The

potentiometer balances the resistor network (VOUT

should equal VREF at DC). The op amp’s common-mode

input voltage is VCM =VIN/2. The error at the input

(VERR) appears at VOUT with a noise gain of 10 V/V.

FIGURE 1-6:

Test Circuit for Dynamic

Input Behavior.

VDD

VOUT

1.001(VDD/3)

0.999(VDD/3)

tSTR

2.2V to 5.5V

2.2V

VIN

VOS

VOS +100 µV

VOS –100 µV

tSTL

VIN

VOUT

VDD

VSS

tODR

VDD/2

VDD

VOUT

VIN

VDD/3

1µF

100 nF

RISO

MCP6V8X

VDD

VOUT

VDD/3

VIN

1µF

100 nF

RISO

MCP6V8X

VDD

VOUT

1µF

RISO

11.0 kΩ

249Ω

11.0 kΩ

500Ω

VIN

VREF =VDD/3

0.1%

25 turn

100 kΩ

0.1%

0 Ω

30 pF

open

100 nF

MCP6V8X

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