HT46C22 datasheet(15/46 Pages) HOLTEK

15 / 46 page

HT46R22/HT46C22

Rev. 1.10

October 2, 2002

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS output or Schmitt trig-

ger input with or without pull-high resistor structures can

be reconfigured dynamically (i.e. on-the-fly) under soft-

ware control. To function as an input, the corresponding

latch of the control register must write

²1². The input

source also depends on the control register. If the con-

trol register bit is

²1², the input will read the pad state. If

the control register bit is

²0², the contents of the latches

will move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H, 17H and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H or 18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. The highest 6-bit of port C and 7-bit of port D are

not physically implemented; on reading them a

²0² is re-

turned whereas writing then results in a no-operation.

See Application note.

Each I/O port has a pull-high option. Once the pull-high

option is selected, the I/O port has a pull-high resistor,

otherwise, there

¢s none. Take note that a non-pull-high

I/O port operating in input mode will cause a floating

state.

The PA3 is pin-shared with the PFD signal. If the PFD

option is selected, the output signal in output mode of

PA3 will be the PFD signal generated by timer/event

counter overflow signal. The input mode always remain-

ing its original functions. Once the PFD option is se-

T M 1

T M 0

T M R

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

T i m e r / E v e n t

C o u n t e r

D a t a B u s

R e l o a d

O v e r f l o w t o I n t e r r u p t

1 / 2

P . D

8 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

P S C 2 ~ P S C 0

Timer/Event Counter

V D D

P . D E N

( P A 3 )

O P 0 ~ O P 7

T M R f o r P A 4 O n l y

I N T f o r P A 5 O n l y

S y s t e m W a k e - u p ( P A o n l y )

R e a d D a t a R e g i s t e r

P A 3

P . D

( P D 0 o r P W M )

C K

C o n t r o l B i t

P U

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P A 0 ~ P A 2

P A 3 / P . D

P A 4 / T M R

P A 5 / I N T

P A 6 , P A 7

P B 0 / A N 0 ~ P B 7 / A N 7

P C 0 ~ P C 1

P D 0 / P W M

Input/output ports

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