Mute

Gx4:Gx0

Function

0

00000

+12dB gain

0

01000

0dB gain

0

01111

34.5dB attenuation

1

XXXXX

mute

Default: 8008h (mono regs.), 8808h (stereo regs.)

Record Select Register (1Ah)

This register independently controls the source for the right

and left channel which will be recorded by the stereo ADC.

The default value is 0000h which corresponds to Mic in.

SL2:SL0

Left Record Source

0

Mic

1

CDIn(L)

2

Video In (L)

3

Aux In (L)

4

Line In (L)

5

Stereo Mix (L)

6

Mono Mix (L)

7

Phone

SR2:SR0

Right Record Source

0

Mic

1

CDIn(R)

2

Video In (R)

3

Aux In (R)

4

Line In (R)

5

Stereo Mix (R)

6

Mono Mix (R)

7

Phone

Record (Input) Gain Register (1Ch)

This register controls the Record (Input) Gain level for the

stereo input selected via the Record Select Control Register

(1Ah). The gain can be programmed from 0dB to +22.5dB in

1.5dB steps. The level for the left and right channel can be

individually controlled. The input can also be muted by set-

ting the MSB to 1.

Mute

Gx3:Gx0

Function

0

1111

22.5dB gain

0

0000

0dB gain

1

XXXX

mute

Default: 8000h

General Purpose Register (20h)

This register controls many miscellaneous functions imple-

mented on the LM4545. The miscellaneous functions in-

clude: POP which allows the PCM to bypass the National 3D

Sound circuitry, 3D which enables or disables the National

3D Sound circuitry, MIX which selects the MONO_OUT

source, MS which selects the microphone mux source and

LPBK which connects the output of the stereo ADC to input

of the stereo DAC. LPBK provides for a digital loopthru path

when enabled.

BIT

Function

POP

PCM out path and mute,0=pre 3D,1=

post 3D

3D

National 3D Sound on / off1=on

MIX

Mono output select0=Mix,1=Mic

MS

Mic select 0 = Mic1 1 = Mic2

LPBK

ADC/DAC loopback

Powerdown Control / Status Register (26h)

This read/write register is used to monitor subsystem readi-

ness and program LM4545 powerdown states. The lower

half of this register is read only with a

″1″ indicated the sub-

section is ready. Writing to the lower 8 bits will have no effect.

When the AC Link

″Codec Ready″ indicator bit (SDATA_IN

slot 0, bit 15) isa1it indicates that the AC Link and AC ’97

registers are in a fully operational state. The AC ’97 Control-

ler must further probe the Powerdown Control / Status Reg-

ister to determine exactly which subsections are ready.

BIT

Function

REF

Vref’s up to nominal level

ANL

Analog mixers ready

DAC

DAC section ready to accept data

ADC

ADC section ready to transmit data

The supported powerdown modes are as follows.

BIT

Function

PRO

PCM in ADC’s and Input Mux powerdown

PR1

PCM out DAC’s powerdown

PR2

Analog Mixer powerdown (VREF still on)

PR3

Analog Mixer powerdown (VREF off)

PR4

Digital Interface (AC Link) powerdown

(external clk off)

PR5

Internal Clk disable

PR6

HP Amp powerdown

Reserved Registers (28h - 7Ah)

Do not write to these registers as they are reserved.

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