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TSP3 Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers |
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TSP3 Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers |
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1 / 2 page  AAL5 SAR with ATM-to-MPLS Interworking Product Overview PortMakerIII firmware provides proven, reliable, and fully supported binary applications for the TSP3 family of devices. The PortMakerIII AAL5 SAR with ATM-to-MPLS interworking application is one of a suite of off-the-shelf applications for the TSP3 hardware platform. It provides up to OC-48 throughput SARing, fine-grained traffic management, ATM- to-MPLS interworking support, and a rich set of value-added features. The firmware is also available with a source code license to allow product differentiation and multi-service operation with other PortMakerIII or custom applications. AAL5 Segmentation and Reassembly (SAR) The PortMakerIII AAL5 application complies with the ITU I.363.5 standard and also conforms to the ATM Forum PICS Proforma for AAL Type 5 tests. The firmware runs across the entire TSP3 family, providing a maximum of 256K connections and up to 2.5 Gbps rates. ATM cell traffic uses either the UTOPIA or POS interfaces for streaming mode operation, while packet traffic can use the POS interface for streaming mode opera- tion, or the PCI bus for shared memory operation. Host-based management of the SAR is accomplished via the PCI bus using commands, acknowledgements, indications, and alarms. Traffic Shaping Traffic shaping is provided at the output of both the segmentation and reassembly functions. In the segmentation direction, each connection has two generic cell rate algo- rithms (GCRAs) that support CBR, VBR, UBR, and UBR+ as defined in the ATM Forum Traffic Management 4.1 Specification. The host selects the shaping parameters and priority on a per VC basis at open channel time. A four-level, strict priority scoreboard-based mechanism is used to schedule cells for transmission, allowing quality of service (QoS) level guarantees. Shaping rates are available from 64 kbps to 100 percent of line rate, within one percent accuracy. Buffer Management Up to 256 Mbytes of local SDRAM are supported for buffering traffic. Two pools of buffers are supported: internal buffers and host buffers. Internal buffers occupy local SDRAM and are 128-bytes in length. Internal buffers are allocated to one of 16 buffer classes during initialization. Host buffers are configurable in size and can be placed either in local SDRAM or in host memory on the PCI bus. Host buffers are optionally used for packet output from the reassembler, when the shared memory mode of operation is used. Congestion Control Segmenter packets are stored in per-VC queues. Queue admission is controlled by one of three methods, selected at open channel time: weighted random early discard (WRED), per-VC flow control, and per-VC EPD. > Runs across entire family of TSP3 devices > ITU I.363.5 compliant AAL5 SAR > ATM Forum TM4.1 traffic shaping > Traffic shaping rates config- urable from 64 kbps to 100 percent of line-rate, within one percent accuracy > Independent shaping and policing profiles for up to 256K connections > Supports up to 64 PHYs at 64 independent rates > Choice of segmenter queue admission policies (WRED, per VC EPD, and per VC flow control) > VP tunnels with WRR and VC tunnels with CBWFQ > ATM-to-MPLS interworking support based on ietf-pwe3- atm-encap > Ingress policing > Auto-VC discovery > Integrated OAM cell processing > Encapsulation / de-encapsulation > Per-PHY and per- connection statistics > PCI based EVM, PortBuilder™™III host driver, and consulting services to accelerate time-to-market > > KE Y FEATURES PortMaker®III AAL5 Firmware TSP3 Traffic Stream Processors |
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