DS1852 datasheet(22/25 Pages) DALLAS

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DS1852

22 of 25

NOTES

1) All voltages are referenced to ground.

2) This is the time for one comparison. The complete cycle is this value multiplied by 3.

3) Absolute voltage error for Bin, Pin, and Rin are valid from 0% to 98%.

4) ASEL = GND, SDA = SCL = Din = Fin = Lin = RSin = VCC.

5) The time to begin monitoring operations after VCC has risen above the analog minimum voltage.

6) After STOP command has been received. No acknowledges will be issued during this interval.

7) A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must

then be met. This will automatically be the case if the device does not stretch the low period of the

SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next

data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

8) After this period, the first clock pulse is generated.

9) The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the

SCL signal.

10) A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of

the SCL signal) in order to bridge the undefined region of the falling edge of SCL.

11) C

B— total capacitance of one bus line in picofarads, timing referenced to 0.9VCC and 0.1VCC.

12) Input levels equal either VCC or GND.

DS1852 Datasheet(PDF) 22 Page - Dallas Semiconductor