1

PS8440C

07/24/01

Pin Description

Product Features

• High Performance Phase-Locked Loop Clock Distribution for

Synchronous DRAM, server and networking applications.

• Zero Input-to-Output delay: Distribute One Clock Input

to four banks of four outputs, with separate output enables

for each bank.

• Allow Clock Input to have Spread Spectrum modulation for

EMI reduction. The clock outputs track the Clock Input

modulation.

• Maximum clock frequency of 150 MHz.

• Low jitter: Cycle-to-Cycle jitter ±100ps max

• Available Packaging:

– 48-pin TSSOP (Thin Shrink Small Outline) (A)

Description

The PI6C2516 family is a low-skew, low jitter, phase-locked loop

(PLL) clock driver, distributing high-frequency clock signals for

SDRAM, server and networking applications. By connecting the

feedback FB_OUT output to the feedback FB_IN input, the propa-

gation delay from the CLK input to any clock output will be nearly

zero. This zero-delay feature allows the CLK input clock to be

distributed, providing 4 banks of four outputs.

to ground.

The PI6C2516 family has the same pinout as the TI CDC2516, with

the added feature of allowing Spread Spectrum clock input.

Block Diagram

CLK

FB_IN

AVCC

4

4Y [0:3]

FB_OUT

4G

PLL

4

3Y [0:3]

3G

4

2Y [0:3]

2G

4

1Y [0:3]

1G

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PI6C2516

Phase-Locked Loop Clock Driver

with 16 Clock Outputs

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

VCC

1Y0

1Y1

GND

GND

1Y2

1Y3

VCC

1G

GND

AVCC

CLK

AGND

AGND

GND

2G

VCC

2Y0

2Y1

GND

GND

2Y2

2Y3

VCC

VCC

4Y0

4Y1

GND

GND

4Y2

4Y3

VCC

4G

GND

AVCC

FB_IN

AGND

FB_OUT

GND

3G

VCC

3Y0

3Y1

GND

GND

3Y2

3Y3

VCC

48-Pin

A