AN1467 datasheet(2/16 Pages) MICROCHIP

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AN1467

DS01467A-page 2

 2012 Microchip Technology Inc.

In the first cycle, Q1 is closed and the current begins to

flow in the primary inductor L1 and through the load via

the coupling capacitor C1 and inductor L2. In the

second cycle, Q2 is closed and the energy stored in the

L2 inductor is delivered to the load. The energy stored

in the main inductor L1 will be reset to its initial value

through the coupling capacitor C1.

The typical waveforms of the ZETA converter are

presented in Figure 3. The continuous current flow on

the load is maintained by the output inductor L2. The

voltage across the main switch (Q1) is the sum of the

input and output voltages as is the case with the SEPIC

converter. The voltage stress across the main switch is

higher and can increase the switching losses of Q1.

The two inductors can be magnetically coupled,

sharing the same magnetic core. This can greatly

reduce the current ripple, as the mutual inductance will

double the apparent value of the inductors.

FIGURE 3:

TYPICAL WAVEFORMS FOR THE ZETA CONVERTER

If the converter operates in Continuous Current Mode

(CCM) and reaches the steady state, the volt-second

balance principle can be applied to determine the DC

transfer function (transformation ratio).

EQUATION 1:

STEADY STATE ANALYZE

EQUATION 2:

VOLT-SECOND BALANCE

The DC transfer function can be found by solving this

system of equations.

EQUATION 3:

DC TRANSFER FUNCTION

For a duty cycle (D) lower than 50%, the ZETA

performs as a buck converter, and for duty cycle higher

than 50%, as the boost converter. As this converter

requires high and low side switches, it can be imple-

mented using drivers developed for the synchronous

buck converter, like the MCP14628. However, some

technical challenges must be solved before using the

MCP14628 synchronous buck driver. As can be seen

from the waveforms, the main switching node (SW)

goes below ground. The typical application for the

MCP14628 synchronous buck converter must be

modified in order to avoid damage of the chip when the

SW node goes below ground.

VL1

VIN

VL2

VIN VC1 VOUT

–

VL1

–

VL2

OUT

–

“On State”

“Off State”

D *V

VC1 VOUT

–



1 D

–

 * V

OUT

–

D * V

1 D

–

 * V

–

OUT

1 D

–

------------- * V

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