TAS5015

SLES017 – SEPTEMBER 2001

7

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functional description (continued)

Initialization Time = 100 ms max

RESET

PDN

VALID_L

VALID_R

Figure 1. Power-Up Timing (RESET Preceding PDN)

Initialization Time = 5 ms max

RESET

PDN

Greater Than 16 MCLK Periods

VALID_L

VALID_R

Figure 2. Power-Up Timing (PDN Preceding RESET)

reset

The reset signal for the TAS5015 must be applied whenever toggling the M_S, DBSPD signal. This reset is

asynchronous. See Figure 3 for reset timing. To initiate the reset sequence the RESET pin is asserted low. As

long as the pin is held low the chip is in the reset state. During this reset time, the PWM outputs are hard-muted

(P-outputs held low and M-outputs held high) and the PWM outputs valid pins (VALID_L. VALID_R) are held

low. Assuming PDN is high, the rising edge of the reset pulse begins chip initialization. After the initialization

time, the TAS5015 begins normal operation.

Initialization

Normal

Operation

RESET

PDN

Normal Operation

5 ms max

VALID_L

VALID_R

Figure 3. Reset Timing

power down

Note that power down is an asynchronous operation. To place the device in total power-down mode, both

RESET and PDN must be held low. As long as these pins are held low, the chip is in the power-down state and

the PWM outputs are hard muted with the P outputs held low and the M outputs held high. To place the device

back into normal mode, see the power up section.

NOTE:

In order for the dynamic logic to be properly powered down, the clocks should not be stopped before

the PDN pin goes low. Otherwise, the device may drain additional supply current.