SX28AC75-ISLASHTQ datasheet(1/52 Pages) ETC

Part #	SX28AC75-I/TQ

Description	Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug

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Manufacturer	ETC [List of Unclassifed Manufacturers]

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Scenix™ and the Scenix logo are trademarks of Scenix Semiconductor, Inc.

I2C™ is a trademark of Philips Corporation

Microwire™ is a trademark of National Semiconductor Corporation

All other trademarks mentioned in this document are property of their respec-

tive companies.

January 19, 2000

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

Configurable Communications Controllers with EE/Flash Program

Memory, In-System Programming Capability and On-Chip Debug

1.0

PRODUCT OVERVIEW

1.1

Introduction

The Scenix SX family of configurable communications

controllers are fabricated in an advanced CMOS process

technology. The advanced process, combined with a

RISC-based architecture, allows high-speed computa-

tion, flexible I/O control, and efficient data manipulation.

Throughput is enhanced by operating the device at fre-

quencies up to 50/75 MHz and by optimizing the instruc-

tion set to include mostly single-cycle instructions. In

addition, the SX architecture is deterministic and totally

reprogramable. The unique combination of these charac-

teristics enables the device to implement hard real-time

functions as software modules (Virtual Peripheral™) to

replace traditional hardware functions.

On-chip functions include a general-purpose 8-bit timer

with prescaler, an analog comparator, a brown-out detec-

tor, a watchdog timer, a power-save mode with multi-

source wakeup capability, an internal R/C oscillator, user-

selectable clock modes, and high-current outputs.

Figure 1-1. Block Diagram

In te rru p t

MIW U

Po rt B

C o m p

P o w er-O n

Re se t

R ESET

8-bit W a tchdo g

Tim er (WD T )

8-bit T im er

RT C C

8

Po rt C

8

Po rt A

8

4

Inte rn al D a ta B u s

In -Syste m

De bu gg ing

In -S yste m

Pro g ra m m in g

2k W o rd s

EEPR O M

S ystem

Clo ck

Brow n -O ut

MIW U

MC L R

OSC

Drive r

4M Hz

In te rn a l

RC O S C

Clock

Sele ct

÷ 4 or ÷ 1

136 Byte s

SR AM

A ddress

Write D ata

R ead D a ta

In structio n

W

FS R

STATU S

PC

MO D E

OPTIO N

System C lock

OS C 1 OS C2

Fe tch

8

12

A ddress

12

8

ALU

8

3

RT C C

An alo g

8

In te rru p t Sta ck

PC

3 L e vel

Decode

Execu tive

W rite Ba ck

IR EAD

Sta ck

Instruction

Pipeline

Pre scale r for R T C C

or

P re sca le r for W D T

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