P83C180 datasheet(39/84 Pages) PHILIPS

39 / 84 page

1997 Dec 12

Philips Semiconductors

Product speciﬁcation

Microcontrollers for monitors with DDC

interface, auto-sync detection and sync proc.

P83Cx80; P87C380

16 DIGITAL-TO-ANALOG CONVERTER (DAC)

Four channels of linear voltage outputs mainly for the

horizontal and vertical position control are provided from

four sets of the Digital-to-Analog Converter (DAC).

The DACs are well tuned to meet the following specific

system requirements of the monitor.

• For a 21'' monitor, the shift per step by changing the data

of the DAC is expected to be 0.5 mm. Accordingly, the

DAC with 8-bit resolution is required.

• To avoid visible position shift due to environmental

temperature change, the drift of output level of the DAC

is less than 1.5 mV/

°C.

• To eliminate the visible jitter, the maximum tolerable

ripple for the output voltage of the DAC is less than

2 mV.

Each DAC comprises an 8-bit data latch, a voltage scaling

mechanism and an output driver.

A precise current reference is provided internally to serve

4 sets of DACs. The voltage sources with values weighted

by 20 up to 27 are switched according to the data input so

that the sum of the selected voltages gives the required

analog voltage from the output driver.

The range of the output voltage is approximately 0 to 5 V.

However, to fulfil some special requirement for current

driving capability, a very minor reduction (0.2 to 0.4 V) of

the output voltage range is acceptable.

The DAC outputs are protected against short-circuits to

VDDA and VSSA. To avoid the possibility of oscillation,

capacitive loading at the DAC outputs should not exceed

10 pF. In reduced power modes like Idle mode and

Power-down mode, the operation of the DACs can be

disabled to save the power consumption. In that case, the

outputs of the DACs are indeterminate.

Figure 20 illustrates the block diagram of the DAC.

16.1

8-bit Data Registers for the DAC outputs

(DACn; n = 0 to 3)

The DACs are individually programmed using an 8-bit

word to select an output from one of 256 voltage steps. For

VDDA = 5 V, the maximum output voltage of all DACs is 5 V

and the resolution is approximately 17.6 mV (5 V/256). At

power-on all DAC outputs are set to their lowest value:

00H (i.e. 0 V). The relevant SFRs for the DACs are

described in Table 33 and 34.

Table 33 8-bit Data Registers for the DAC outputs (address E9H to ECH)

Table 34 Description of DACn bits

76543210

DACn.7

DACn.6

DACn.5

DACn.4

DACn.3

DACn.2

DACn.1

DACn.0

BIT

SYMBOL

DESCRIPTION

7 to 0

DACn.7 to DACn.0

8-bit data for the DAC; channel n (n=0to3).

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