P87C51RC2FN datasheet(32/67 Pages) PHILIPS

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Philips Semiconductors

Product data

P87C51RA2/RB2/RC2/RD2

80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP

with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high

speed (30/33 MHz)

2003 Jan 24

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register when set disables the

ALE output unless the CPU needs to perform an off-chip memory

access.

Reduced EMI Mode

AUXR (8EH)

–

EXTRAM

AUXR.1

EXTRAM

AUXR.0

See more detailed description in Figure 32.

Dual DPTR

The dual DPTR structure (see Figure 18) is a way by which the chip

will specify the address of an external data memory location. There

are two 16-bit DPTR registers that address the external memory,

and a single bit called DPS = AUXR1/bit0 that allows the program

code to switch between them.

• New Register Name: AUXR1#

• SFR Address: A2H

• Reset Value: xxxxxxx0B

AUXR1 (A2H)

43210

–

GF2

–

DPS

Where:

DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.

Select Reg

DPS

DPTR0

DPTR1

The DPS bit status should be saved by software when switching

between DPTR0 and DPTR1.

The GF2 bit is a general purpose user-defined flag. Note that bit 2 is

not writable and is always read as a zero. This allows the DPS bit to

be quickly toggled simply by executing an INC AUXR1 instruction

without affecting the GF2 bit.

DPS

DPTR1

DPTR0

DPH

(83H)

DPL

(82H)

EXTERNAL

DATA

MEMORY

SU00745A

BIT0

AUXR1

Figure 18.

DPTR Instructions

The instructions that refer to DPTR refer to the data pointer that is

currently selected using the AUXR1/bit 0 register. The six

instructions that use the DPTR are as follows:

INC DPTR

Increments the data pointer by 1

MOV DPTR, #data16

Loads the DPTR with a 16-bit constant

MOV A, @ A+DPTR

Move code byte relative to DPTR to ACC

MOVX A, @ DPTR

Move external RAM (16-bit address) to

ACC

MOVX @ DPTR , A

Move ACC to external RAM (16-bit

address)

JMP @ A + DPTR

Jump indirect relative to DPTR

The data pointer can be accessed on a byte-by-byte basis by

specifying the low or high byte in an instruction which accesses the

SFRs. See

Application Note AN458 for more details.

P87C51RC2FN Datasheet(PDF) 32 Page - NXP Semiconductors

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