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AD8556ACPZ-R2 Datasheet(PDF) 21 Page - Analog Devices |
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AD8556ACPZ-R2 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 28 page ![]() AD8556 Data Sheet CODE 0 1 0 0 1 1 WAVEFORM tW0 tWS tW0 tWS tWS tWS tW0 tWS tW1 tW1 tW1 Figure 49. Timing Diagram for Code 010011 Table 10. Timing Specifications Timing Parameter Description Specification tw0 Pulse width for loading 0 into shift register Between 50 ns and 10 µs tw1 Pulse width for loading 1 into shift register ≥50 µs tws Width between pulses ≥10 µs Table 11. 38-Bit Serial Word Format Field No. Bits Description 0 0 to 11 12-Bit Start of Packet 1000 0000 0001 1 12 to 13 2-Bit Function 00: Change Sense Current 01: Simulate Parameter Value 10: Program Parameter Value 11: Read Parameter Value 2 14 to 15 2-Bit Parameter 00: Second Stage Gain Code 01: First Stage Gain Code 10: Output Offset Code 11: Other Functions 3 16 to 17 2-Bit Dummy 10 4 18 to 25 8-Bit Value Parameter 00 (Second Stage Gain Code): 3 LSBs Used Parameter 01 (First Stage Gain Code): 7 LSBs Used Parameter 10 (Output Offset Code): All 8 Bits Used Parameter 11 (Other Functions) Bit 0 (LSB): Master Fuse Bit 1: Fuse for Production Test at Analog Devices Bit 2: Parity Fuse 5 26 to 37 12-Bit End of Packet 0111 1111 1110 A 38-bit serial word is used, divided into 6 fields. Assuming each bit can be loaded in 60 µs, the 38-bit serial word transfers in 2.3 ms. Table 11 summarizes the word format. Field 0 and Field 5 are the start-of-packet field and end-of- packet field, respectively. Matching the start-of-packet field with 1000 0000 0001 and the end-of-packet field with 0111 1111 1110 ensures that the serial word is valid and enables decoding of the other fields. Field 3 breaks up the data and ensures that no data combination can inadvertently trigger the start-of-packet and end-of-packet fields. Field 0 should be written first and Field 5 written last. Within each field, the MSB must be written first and the LSB written last. The shift register features power-on reset to minimize the risk of inadvertent programming; power-on reset occurs when VDD is between 0.7 V and 2.2 V. Rev. B | Page 20 of 27 |
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