AD9163BBCZ datasheet(35/124 Pages) AD

35 / 124 page

AD9163

Data Sheet

Rev. 0 | Page 34 of 123

Figure 95 and Figure 96 are provided as points of reference for

hardware designers and show the insertion loss for various

lengths of well laid out stripline and microstrip transmission

lines, respectively. See the Hardware Considerations section for

specific layout recommendations for the JESD204B channel.

Low power mode is recommended if the insertion loss of the

JESD204B PCB channels is less than that of the most lossy

supported channel for low power mode (shown in Figure 93). If

the insertion loss is greater than that, but still less than that of

the most lossy supported channel for normal mode (shown in

Figure 93), use normal mode. At 12.5 Gbps operation, the

equalizer in normal mode consumes about 4 mW more power

per lane used than in low power equalizer mode. Note that either

mode can be used in conjunction with transmitter preemphasis

to ensure functionality and/or optimize for power.

–40

–35

–30

–25

–20

–15

–10

–5

FREQUENCY (GHz)

STRIPLINE = 6"

STRIPLINE = 10"

STRIPLINE = 15"

STRIPLINE = 20"

STRIPLINE = 25"

STRIPLINE = 30"

Figure 95. Insertion Loss of 50 Ω Striplines on FR4

–40

–35

–30

–25

–20

–15

–10

–5

FREQUENCY (GHz)

6" MICROSTRIP

10" MICROSTRIP

15" MICROSTRIP

20" MICROSTRIP

25" MICROSTRIP

30" MICROSTRIP

Figure 96. Insertion Loss of 50 Ω Microstrips on FR4

DATA LINK LAYER

The data link layer of the AD9163 JESD204B interface accepts

the deserialized data from the PHYs and deframes and descrambles

them so that data octets are presented to the transport layer to be

put into DAC samples. The architecture of the data link layer is

shown in Figure 97. The data link layer consists of a

synchronization FIFO for each lane, a crossbar switch, a deframer,

and a descrambler.

The AD9163 can operate as a single-link high speed JESD204B

serial data interface. All eight lanes of the JESD204B interface

handle link layer communications such as code group synch-

ronization (CGS), frame alignment, and frame synchronization.

The AD9163 decodes 8-bit/10-bit control characters, allowing

marking of the start and end of the frame and alignment

between serial lanes. Each AD9163 serial interface link can issue

a synchronization request by setting its SYNCOUT± signal low.

The synchronization protocol follows Section 4.9 of the JESD204B

standard. When a stream of four consecutive /K/ symbols is

received, the AD9163 deactivates the synchronization request

by setting the SYNCOUT± signal high at the next internal

LMFC rising edge. Then, the AD9163 waits for the transmitter

to issue an initial lane alignment sequence (ILAS). During the

ILAS, all lanes are aligned using the /A/ to /R/ character transition

as described in the JESD204B Serial Link Establishment section.

Elastic buffers hold early arriving lane data until the alignment

character of the latest lane arrives. At this point, the buffers for

all lanes are released and all lanes are aligned (see Figure 98).

AD9163BBCZ Datasheet(PDF) 35 Page - Analog Devices

AD9163BBCZ Datasheet(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL