X1228 datasheet(20/31 Pages) XICOR

20 / 31 page

X1228

REV 1.3 3/24/04

Characteristics subject to change without notice.

20 of 31

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Figure 10. Slave Address, Word Address, and Data Bytes (64 Byte pages)

Write Operations

Byte Write

For a write operation, the device requires the Slave

Address Byte and the Word Address Bytes. This gives

the master access to any one of the words in the array

or CCR. (Note: Prior to writing to the CCR, the master

must write a 02h, then 06h to the status register in two

preceding operations to enable the write operation.

See “Writing to the Clock/Control Registers.” Upon

receipt of each address byte, the X1228 responds with

an acknowledge. After receiving both address bytes

the X1228 awaits the eight bits of data. After receiving

the 8 data bits, the X1228 again responds with an

acknowledge. The master then terminates the transfer

by generating a stop condition. The X1228 then begins

an internal write cycle of the data to the nonvolatile

memory. During the internal write cycle, the device

inputs are disabled, so the device will not respond to

any requests from the master. The SDA output is at high

impedance. See Figure 11.

Figure 11. Byte Write Sequence

Figure 12. Writing 30 bytes to a 64-byte memory page starting at address 40.

Slave Address Byte

Byte 0

Data Byte

Byte 3

000

R/W

Device Identifier

Array

CCR

Word Address 1

Byte 1

Word Address 0

Byte 2

Slave

Address

Word

Address 1

Data

SDA Bus

Signals From

The Slave

Signals from

the Master

Word

Address 0

000 00 0 0

Address

23 Bytes

7 Bytes

Address

= 6

Address Pointer

Ends Here

Addr = 7

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