CS82C37A datasheet(12/23 Pages) HARRIS

12 / 23 page

4-203

82C37A

Application Information

Figure 6 shows an application for a DMA system utilizing the

82C37A DMA controller and the 80C88 Microprocessor. In

this application, the 82C37A DMA controller is used to

improve system performance by allowing an I/O device to

transfer data directly to or from system memory.

Components

The system clock is generated by the 82C84A clock driver

and is inverted to meet the clock high and low times required

by the 82C37A DMA controller. The four OR gates are used

to support the 80C88 Microprocessor in minimum mode by

producing the control signals used by the processor to

access memory or I/O. A decoder is used to generate chip

select for the DMA controller and memory. The most signiﬁ-

cant bits of the address are output on the address/data bus.

Therefore, the 82C82 octal latch is used to demultiplex the

address. Hold Acknowledge (HLDA) and Address Enable

(AEN) are “ORed” together to insure that the DMA controller

does not have bus contention with the microprocessor.

Operation

A DMA request (DREQ) is generated by the I/O device. After

receiving the DMA request, the DMA controller will issue a

Hold request (HRQ) to the processor. The system busses

are not released to the DMA controller until a Hold Acknowl-

edge signal is returned to the DMA controller from the

80C88 processor. After the Hold Acknowledge has been

received, addresses and control signals are generated by

the DMA controller to accomplish the DMA transfers. Data is

transferred directly from the I/O device to memory (or vice

versa) with IOR and MEMW (or MEMR and IOW) being

active. Note that data is not read into or driven out of the

DMA controller in I/O-to-memory or memory-to-I/O data

transfers.

FIGURE 6. APPLICATION FOR DMA SYSTEM

MEMR

MEMW

IOR

IOW

MEMCS

MEMR

MEMW

MEMORY

47k

Ω

VCC

ADDRESS BUS

DATA BUS

VCC

DATA BUS

80C88

M/IO

HRQ

HLDA

ALE

AD0

AD7

MN/MX

CLK

82C84A

82C85

HLDA

MEMCS

STB

82C82

DECODER

ADDRESS BUS

STB

82C82

A0-7

CLK

EOP

HLDA

IOR

DACK

ADSTB

AEN

DB0-7

IOW

MEMR

MEMW

HRQ

DREQ0

82C37A

IOR

IOW

VCC

DREQ

I/O

DEVICE

NOTE:

The address lines need pull-up resistors.

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