MAX77301EVKIT datasheet(5/15 Pages) MAXIM

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Evaluates: MAX77301

MAX77301 Evaluation Kit

LED Indicators

UOK Status Output

UOK is an open-drain output that is pulled low when

the BUS input is inserted and adapter-type detection is

complete. In USB suspend mode, the UOK pin flashes

with a duty cycle of 50% for a duration of 1.5s. When

D+/D- open is detected and bit nENU_EN = 1, UOK

flashes with a duty cycle of 50% for a duration of 0.15s.

UOK is in high impedance if no adapter is detected.

The input UVLO/OVLO thresholds must be met prior to

adapter detect and UOK pin response. The UVLO/OVLO

thresholds are shown in Table 3.

CHG_TYPE Status Output

CHG_TYPE is an open-drain output that indicates the

type and current limit of the external power supply. The

pin is pulled low to indicate a 100mA USB 2.0 host with

device input-current limit (ILIM) ≤ 100mA. CHG_TYPE is

high impedance when the device input-current limit (ILIM)

is ≥ 500mA.

EXT_PWRON Output

EXT_PWRON is an active-low, open-drain output that is

pulled low after a valid external power supply is present.

If a valid power supply is not present, EXT_PWRON is in

high impedance.

The EXT_PWRON output can be connected to an exter-

nal device that controls power to external circuits, such

as an external p-channel MOSFET. If a valid adapter is

connected to the system while the battery is below the

VBAT_UVLO threshold, EXT_PWRON transitions from

high impedance to low when the adapter type is deter-

mined and UOK transitions from high to low impedance.

Charge Status Output (CHG_STAT)

CHG_STAT is an active-low, open-drain output indicat-

ing state-of-battery charging. A temperature or timer fault

changes the charge state of the CHG_STAT pin. See

Table 4 for CHG_STAT behaviors.

Interrupt Request Output (IRQ)

IRQ is an active-low, open-drain output that is pulled low

when an interrupt occurs. If an interrupt has occurred, the

event and status information is available in the EVENT_

and STATUS_ registers. Interrupts indicate temperature

and voltages as well as charge and timer fault conditions.

Events are triggered by a state change in the associated

tion when read by the I2C interface. When the EVENT_

registers are read in page mode, the IRQ is not released

until the last bit has been read. New interrupt events are

held until a complete read of all registers has occurred.

The interrupt mask bits located in register 0x07 disable

the output pin, maintaining a high-impedance state.

Table 3. UVLO/OVLO Thresholds

Table 4. CHG_STAT Indications

FOR

UVLO

OVLO

Initial BUS detection

4.0V (typ) rising

6.9V (typ) (VBUS rising)

USB 2.0 low power

3.9V (typ) falling

USB 2.0 high power, or when ILIM is not set to 111

4.1V (typ) falling

Adaptive (when ILIM is set to 111)

VSYS + 50mV (typ) falling

CHARGER STATUS

CHG_STAT BEHAVIOR

Charge in progress, low (continuous)

Charge suspend (due to temperature faults) pulses with 1.5s

duration and 50% duty cycle

Charge suspend (due to temperature faults) pulses with 1.5s

duration and 50% duty cycle

Charge suspend (due to temperature faults) pulses with 1.5s

duration and 50% duty cycle

Charge suspend (due to temperature faults) pulses with 1.5s

duration and 50% duty cycle

Timer fault pulses with 0.15s duration and 50% duty cycle

Charge done, high impedance

Battery removed pulses with 0.1s duration

10% to 20% duty cycle

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