MICRF008

Micrel

MICRF008

6

July 2003

Data Slicing Level

Extraction of the DC value of the demodulated signal for

purposes of logic-level data slicing is accomplished by an

external capacitor C

resistor RSC, indicated in the block diagram. The effective

resistance of RSC scales inversely proportional to REFOSC

frequency. The nominal value of RSC given in the “

Electrical

Ω for a REFOSC frequency of

3.36MHz. Slicing level time constant value vary depending

on data pattern, data rate and data duty cycle.

Automatic Gain Control (AGC)

The signal path has automatic gain control (AGC) to increase

the overall receiver dynamic range. An external capacitor,

C

Normally the C

start-up times are required when the receiver is first powered-

on, the C

of decay-to-attack time constant is fixed at 10:1 (that is, the

the user cannot change this ratio. Nevertheless, the attack

time constant is set externally by choosing a value for C

Another function of the AGC control voltage is to raise the

noise floor in order to guarantee a clean signal between the

preamble and the data, sometimes called dead time. The

AGC control voltage can be further manipulated and ampli-

fied to create an RSSI signal, which is useful for several

different applications.

Reference Oscillator

All timing and tuning operations on the MICRF008BM are

derived from the internal Colpitts reference oscillator. The

reference frequency can be implemented in two ways, by

using a resonator device (a ceramic resonator or crystal), or

by driving an external signal, which should not exceed

0.5V

RF carrier frequency by 129.

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF008 is

shown in Figures 1 through 6. Specific information regarding

each of these circuits is discussed in the following sub-

paragraphs. Not shown are ESD protection diodes which are

applied to all input pins.

C

Figure 2 illustrates the C

driven from a P-Channel MOSFET source-follower biased

with approximately 20

µA of bias current. Transmission gates

TG1 and TG2 isolate the 3.3pF capacitor. Internal control

signals PHI1/PHI2 are related in a manner such that the

impedance across the transmission gates looks like a “resis-

tance.” The DC potential on the C

2.2V, fundamentally determined by the VGS of the two P-

Channel MOSFET source-followers shown.

C

Figure 3 illustrates the C

control voltage is developed as an integrated current into a

capacitor C

1.5

µA. Signal gain of the RF/IF strip inside the IC diminishes

as the voltage on C

capacitor to C

fixed at 1:10.

VDDBB

VSSBB

Compa-

rator

1.5

µA

15

µA

CAGC

Figure 3. C

3.3pF

PHI2B

TG1

TG2

PHI1B

PHI1

PHI2

CTH

DC-coupled

Switched

Cap. Filter

VDDBB

VSSBB

VSSBB

20

µA

VDDBB

VSSBB

20

µA

Demod

Signal

(0Vdc)

Figure 2. C