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LM95010 Datasheet(PDF) 14 Page - National Semiconductor (TI) |
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LM95010 Datasheet(HTML) 14 Page - National Semiconductor (TI) |
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14 / 19 page ![]() 2.0 Register Set (Continued) 2.6 CAPABILITIES FIXED (Addr 03o) Reg Add Register Name R/ W P O R Val Bit 15 MSb Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSb 000 011 Capabilities Fixed R1h Reserved FuncDescriptor1 0000000000000001 The value of this register defines the capabilities of the LM95010. The LM95010 supports only one function, that of Temperature Measurement type. Please refer to the SensorPath specification for further details on other FuncDescriptor values. 2.7 DEVICE STATUS (Addr 04o) This register is set to the reset value by a Device Reset. Reg Add Register Name R/ W P O R Val Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSb 000 100 Device Status R 0h BER 0 0 ERF1 0 0 0 SF1 Bit Type Description 0RO SF1 (Status Function 1). This bit is set by a Function Event within Function 1. Event details are function dependent and are described within the function. SF1 is cleared by Device Reset or by handling the event within the function (see Section 2.9 for further details). 0: Status flag for Function 1 is inactive (no event). 1: Status flag for Function 1 is active indicating that a Function Event has occurred. 3-1 RO Not supported. Will always read "0". 4RO ERF1 (Error Function 1) This bit is set in response to an error indication within Function 1. ERF1 is cleared by Device Reset or by handling the error condition within the function (see Section 2.9 for further details). 0: No error occurred in Function 1. 1: Error occurred in Function 1. 6-5 RO Not supported. Will always read "0". 7RO BER (Bus Error). This bit is set when the device either generates, or receives an error indication in the ACK bit of the transaction (i.e., no-acknowledge). BER is cleared by Device Reset or by reading the Device Status register. 0: No transaction error occurred. 1: An ACK bit error (no-acknowledge) occurred during the last transaction. 2.8 DEVICE CONTROL (Addr 05o) This register responds to a broadcast write command (DeviceNumber 000). Write using broadcast address is ignored by bits 15-2. This register is set to the reset value by a Device Reset. Reg Add Register Name R/ W P O R Val Bit 15 MSb Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSb 000 101 Device Control R/ W 0h Reserved EnF1 Res Low Pwr Shut down Re set 00000000000 Bit Type Description 0 R/W Reset (Device Reset). When set to "1" this bit initiates a Device Reset operation ( See Section 2.2). This bit self-clears after the Device Reset operation is completed. 0: Normal device operation. (default) 1: Device Reset The LM95010 does not require a Device Reset command after power. www.national.com 14 |
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