74ACT11377

OCTAL D-TYPE FLIP-FLOP

WITH CLOCK ENABLE

SCAS129 – D3450, MARCH 1990 – REVISED APRIL 1993

POST OFFICE BOX 655303

Copyright

2–1

Clocking

Buffer/Storage Registers

Shift Registers

Pattern Generators

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

mm Process

at 125

°C

Small-Outline Packages, Plastic Shrink

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

These circuits are positive-edge-triggered D-type flip-flops with a clock enable input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and

is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high

or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking

by transitions at the CLKEN input.

The 74ACT11377 is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLKEN

CLK

D

Q

H

X

X

Q0

L

↑

HH

L

↑

LL

X

L

X

Q0

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

1Q

2Q

3Q

4Q

GND

GND

GND

GND

5Q

6Q

7Q

8Q

CLKEN

1D

2D

3D

4D

5D

6D

7D

8D

CLK

DB, DW OR NT PACKAGE

(TOP VIEW)

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.