Application Notes

Thermal Management

The LMH6672 is a high-speed, high power, dual operational

amplifier with a very high slew rate and very low distortion.

For ease of use, it uses conventional voltage feedback.

These characteristics make the LMH6672 ideal for applica-

tions where driving low impedances of 25-100

Ω such as

xDSL and active filters.

A class AB output stage allows the LMH6672 to deliver high

currents to low impedance loads with low distortion while

consuming low quiescent supply current. For most op-amps,

class AB topology means that internal power dissipation is

rarely an issue, even with the trend to smaller surface mount

packages. However, the LMH6672 has been designed for

applications where high levels of power dissipation may be

encountered.

Several factors contribute to power dissipation and conse-

quently higher junction temperatures. These factors need to

be well understood if the LMH6672 is to perform to specifi-

cations in all applications. This section will examine the

typical application that is shown on the front page of this data

sheet as an example. (Figure 1) Because both amplifiers are

in a single package, the calculations will for the total power

dissipated by both amplifiers.

There are two separate contributors to the internal power

dissipation:

1. The product of the supply voltage and the quiescent

current when no signal is being delivered to the external

load.

2. The additional power dissipated while delivering power

to the external load.

The first of these components appears easy to calculate

simply by inspecting the data sheet. The typical quiescent

supply current for this part is 6.2mA per amplifier, therefore,

with a (6 volt supply, the total power dissipation is:

P

(V

With a thermal resistance of 172˚C/W for the SOIC package,

this level of internal power dissipation will result in a junction

temperature (T

Using the worst-case maximum supply current of 18mA and

an ambient of 85˚C, a similar calculation results in a power

dissipation of 216 mW, or a T

This is approaching the maximum allowed T

fore a signal is applied. Fortunately, in normal operation, this

term is reduced, for reasons that will soon be explained.

The second contributor to high T

internally when power is delivered to the external load. This

cause of temperature rise is more difficult to calculate, even

when the actual operating conditions are known.

To maintain low distortion, in a Class AB output stage, an idle

current, I

is maintained through the output transistors

when there is little or no output signal. In the LMH6672,

about 4.8 mA of the total quiescent supply current of 12.4 mA

flows through the output stages.

Under normal large signal conditions, as the output voltage

swings positive, one transistor of the output pair will conduct

the load current, while the other transistor shuts off, and

dissipates no power. During the negative signal swing this

situation is reversed, with the lower transistor sinking the

load current while the upper transistor is cut off. The current

in each transistor will approximate a half wave rectified

version of the total load current.

Because the output stage idle current is now routed into the

load, 4.8mA can be subtracted from the quiescent supply

current when calculating the quiescent power when the out-

put is driving a load.

The power dissipation caused by driving a load in a DSL

application, using a 1:2 turns ratio transformer driving 20

mW into the subscriber line and 20mW into the back termi-

nation resistors, can be calculated as follows:

P

P

P

P

tors

P

At full specified power, P

xI

In this application, V

I

I

idle current.

I

A

turns ratio transformer, is

= 28.28mA RMS.

For a Gaussian signal, which the DMT ADSL signal approxi-

mates, A

= 22.6mA. Therefore, P

TOT

= (22.6mA + 7.6mA) x 12V = 362mW and P

= 322mW.

In the SOIC package, with a

θ

temperature rise of 55˚C. With an ambient temperature at

the maximum recommended 85˚C, the T

below the specified 150˚C maximum.

Even if we assume the absolute maximum I

ture of 18mA, when we scale up the I

the P

147˚C.

Although very few CPE applications will ever operate in an

environment as hot as 85˚C, if a lower T

LMH6672 is to be used in an application where the power

dissipation is higher, the PSOP package provides a much

lower

θ

Using the same P

ture rise is only 19˚ and 21˚C, resulting in T

ambient of 104˚C and 106˚C respectively.

Circuit Layout Considerations

National Semiconductor suggests the following evaluation

boards as a guide for high frequency layout and as an aid in

device testing and characterization. Since the exposed PAD

(or DAP) of the PSOP and LLP package is internally floating,

the footprint for DAP could be connected to ground plane in

PCB for better heat dissipation.

Device

Package

Evaluation

Board PN

LMH6672MA

8-Pin SOIC

CLC730036

LMH6672LD

8-Pin LLP

CLC730114

LMH6672MR

8-Pin PSOP

CLC730121

These free evaluation boards are shipped when a device

sample request is placed with National Semiconductor.

www.national.com

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