3.1.3 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)

(IF_R[2]-[16])

IF_R_CNTR/RF_R_CNTR

Divide Ratio

14

13

12

11

109876543210

3

00000

0000000011

4

00000

0000000100

-

-----

----------

32,767

11111

1111111111

Notes: Divide ratio: 3 to 32,767 (Divide ratios less than 3 are prohibited).

RF_R_CNTR/IF_R_CNTR These bits select the divide ratio of the programmable reference dividers.

3.1.4 IF_CP_WORD

(IF_R[17]-[18])

IF_CP_WORD

(IF_R [17] - [18] )

CP_GAIN_8

IF_PD_POL

BIT

LOCATION

FUNCTION

0

1

CP_GAIN_8

IF_R [18]

IF Charge Pump Current Gain

1X

8X

IF_PD_POL

IF_R [17]

IF Phase Detector Polarity

Negative

Positive

CP_GAIN_8 is used to toggle the IF charge pump current magnitude between 1x mode (100 uA typ) and 8x mode (800uA typ).

IF_PD_POL is set to one when IF VCO characteristics are positive. When IF VCO frequency decreases with increasing control

voltage IF_PD_POL should set to zero.

3.1.5 FoLD* Programming Truth Table

(IF_R[19]-[21])

FoLD

Fo/LD OUTPUT STATE

0 0 0

IF and RF Analog Lock Detect (Open Drain)

1 0 0

IF Digital Lock Detect

0 1 0

RF Digital Lock Detect

1 1 0

IF and RF Digital Lock Detect

0 0 1

IF R counter

1 0 1

IF N counter

0 1 1

RF R counter

1 1 1

RF N counter

*FoLD - Fout/Lock Detect PROGRAMMING BITS

3.2 RF_R Register

If the Control Bits (CTL [1:0]) are 1 0, data is transferred from the 24-bit shift register into the RF_R register latch which sets the

RF PLL 15-bit R counter divide ratio. The divide ratio is programmed using the RF_R_CNTR word as shown in table 3.1.3. The

divide ratio must be

≥ 3. The bits used to control the voltage doubler (V2_EN) and RF Charge Pump (RF_CP_WORD) are

detailed in 3.2.2.

MSB

LSB

DLL_MODE

V2_EN

RF_CP_WORD [4:0]

RF_R_CNTR [14:0]

1

0

23

22

21

17

16

2

1

0

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