2.4.4 The FoLD Output Truth Table

Main

R[18]

Aux

R[18]

Main

R[19]

Aux

R[19]

Fo/LD Output State

0

0

0

0

Disabled

0

1

0

0

Aux Lock Detect (Note 9)

1

0

0

0

Main Lock Detect (Note 9)

1

1

0

0

Main/Aux Lock Detect (Note 9)

X

0

0

1

Aux Reference Divider Output

X

0

1

0

Main Reference Divider Output

X

1

0

1

Aux Programmable Divider Output

X

1

1

0

Main Programmable Divider Output

0

0

1

1

FastLock Output. Open Drain Output (Note 10)

0

1

1

1

Reset Aux R and N Counters and TRI-STATE Aux Charge Pump (Note 11)

1

0

1

1

Reset Main R and N Counters and TRI-STATE Main Charge Pump (Note

11)

1

1

1

1

Reset All Four Counters and TRI-STATE both Charge Pumps (Note 11)

X - don’t care condition

Note 9: Open drain lock detect output is provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the

pin is HIGH, with narrow pulses LOW. In the Main/Aux lock detect mode a locked condition is indicated when Main and Aux are both locked.

Note 10: The FastLock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during FastLock operation. Activation of FastLock

Note 11: Aux and Main PLLs can be reset independently from each other by using the R[18] and R[19] bits. The Aux Counter Reset mode resets Aux PLL’s R and

N counters and brings Aux charge pump output to TRI-STATE condition. The Main Counter Reset mode resets Main PLL’s R and N counters and brings Main charge

pump output to a TRI-STATE condition. The Aux and Main Counter Reset modes reset all counters and bring both charge pump outputs to a TRI-STATE condition.

Upon removal of the Reset bits, the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.)

2.5 Serial Data Input Timing

Serial Data Input Timing

DS101026-6

NOTES: Parenthesis data indicates programmable reference divider data.

Data shifted into register on clock rising edge.

Data is shifted in MSB first.

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