Philips Semiconductors

Product data

PCK2022RA

CK00 (100/133 MHz) spread spectrum differential

system clock generator

2003 Jul 31

4

BLOCK DIAGRAM

14.318 MHz

OSC

XIN

XOUT

USB PLL

PWRDWN

PWRDWN

PWRDWN

PWRDWN

PWRDWN

SYS PLL

LOGIC

SPREAD

MULTSEL0

REF[0] (14.318 MHz)

48MHz[0..1] (3 V)

HOST[0..7] (100/133 MHz)

HOST_BAR[0..7] (100/133 MHz)

IOCLK (33/66 MHz)

SW00666

MULTSEL1

PWRDWN

SEL100/133

IBIAS

SELA/B

SELC

FUNCTION TABLE

SEL100/133

SELA

SELB

SELC

HOST

48MHz

IOCLK

REFCLK

0

0

0

0

100 MHz

48 MHz

33.3 MHz

14.318 MHz

0

0

0

1

100 MHz

48 MHz

66.7 MHz

14.318 MHz

0

0

1

0

100 MHz

Hi-Z

33.3 MHz

14.318 MHz

0

0

1

1

100 MHz

Hi-Z

66.7 MHz

14.318 MHz

0

1

0

0

100 MHz

Hi-Z

LOW

LOW

0

1

0

1

100 MHz

33.3 MHz

14.318 MHz

0

1

1

0

LOW

Hi-Z

Hi-Z

Hi-Z

0

1

1

1

100 MHz

66.7 MHz

14.318 MHz

1

0

0

0

133 MHz

48 MHz

33.3 MHz

14.318 MHz

1

0

0

1

133 MHz

48 MHz

66.7 MHz

14.318 MHz

1

0

1

0

133 MHz

Hi-Z

33.3 MHz

14.318 MHz

1

0

1

1

133 MHz

Hi-Z

66.7 MHz

14.318 MHz

1

1

0

0

200 MHz

48 MHz

33.3 MHz

14.318 MHz

1

1

0

1

133 MHz

33.3 MHz

14.318 MHz

1

1

1

0

TCLK/2

TCLK/4

TCLK/4

TCLK

1

1

1

1

133 MHz

66.7 MHz

14.318 MHz

NOTE:

1. These frequencies are for debug, and thus can vary a small amount from the values listed at the vendor’s discretion.