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TDA8757 Datasheet(PDF) 2 Page - NXP Semiconductors |
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TDA8757 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 37 page ![]() Philips Semiconductors TDA8757 Triple 8-bit ADC 170 Msps Preliminary data Rev. 07 — 28 February 2002 2 of 37 9397 750 09457 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 3. Applications s RGB/YUV high-speed digitizing s LCD panels drive s LCD projection systems s VGA to UXGA (1600 × 1200 at 60 Hz) modes. 4. Quick reference data Table 1: Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCCA analog supply voltage for PLL and the RGB channels 4.75 5.0 5.25 V VDDD logic supply voltage for I2C-bus and 3W-bus 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage for PLL and the RGB channels 4.75 5.0 5.25 V VCCA(PLL) analog PLL supply voltage 4.75 5.0 5.25 V VCCO(PLL) output PLL supply voltage 4.75 5.0 5.25 V ICCA analog supply current for the RGB channels − 135 − mA IDDD logic supply current for I2C-bus and 3W-bus − 1 − mA ICCD digital supply current − 95 − mA ICCO output stages supply current − 80 − mA ICCA(PLL) analog PLL supply current − 34 − mA fclk clock frequency normal (Dmx = 0) −− 110 MHz de-multiplexed (Dmx = 1) −− 170 MHz fref(PLL) PLL reference clock frequency 15 − 150 kHz fPLL output clock frequency range 10 − 170 MHz INL DC integral non-linearity from analog input to digital output; full-scale; sinusoidal input; fclk = 170 MHz −±0.5 ±1.5 LSB DNL DC differential non-linearity from analog input to digital output; full-scale; sinusoidal input; fclk = 170 MHz −±0.4 ±1 LSB ∆Gamp/∆T amplifier gain stability variation with temperature Vref = 2.5 V with 100 ppm/ °C maximum − 325 − ppm/ °C B amplifier bandwidth −3 dB; T amb =25 °C 250 −− MHz tset(ADC+AGC) settling time of the block ADC + AGC input signal settling time <1 ns; settling to 1%; fi = 85 MHz − 4 − ns |
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