TMS55166 datasheet(32/70 Pages) TI

32 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

256-/512-bit compatibility of split-register programmable stop point

The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the

CBRS cycle is initiated, the stop-point mode becomes active. In the stop-point mode, and only in the stop-point

mode, the column-address bits AY7 and AY8 are internally swapped to assure compatibility (see Figure 29).

This address-bit swap applies to the column address, and it is effective for all DRAM and transfer cycles. For

example, during the split-register-transfer cycle with stop point, column-address bit AY8 is a don’t care and AY7

decodes the DRAM row half for the split-register-transfer. During stop-point mode, a CBR ( option reset ) cycle

is not recommended because this ends the stop-point mode and restores address bits AY7 and AY8 to their

normal functions. Consistent use of CBR cycles ensures that the TMS551xx remains in nomal mode.

512

× 512

Memory Array

256 - Bit

Data Register

AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1

255

AY8 = 0

AY8 = 1

512

× 512

Memory Array

256 - Bit

Data Register

AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1

255

AY8 = 0

AY8 = 1

NON STOP-POINT MODE

STOP-POINT MODE

Figure 29. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point

IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately

after the power-up initialization cycles are performed.

power up

To achieve proper device operation, an initial pause of 200

µs is required after power up followed by a minimum

of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two

SC cycles are required to initialize the SAM port.

After initialization, the internal state of the TMS551xx is as follows:

STATE AFTER INITIALIZATION

QSF

Write mode

Write-mask register

Color register

Serial-register tap point

SAM port

Defined by the transfer cycle during initialization

Nonpersistent mode

Undefined

Defined by the transfer cycle during initialization

Output mode

TMS55166 Datasheet(PDF) 32 Page - Texas Instruments

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