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AD5162

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TIMING CHARACTERISTICS—ALL VERSIONS

Table 3. VDD = +5 V ± 10%, or +3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

SPI INTERFACE TIMING CHARACTERISTICS9 (Specifications Apply to All Parts)

Clock Frequency

fCLK

MHz

Input Clock Pulse Width

tCH, tCL

Clock level high or low

Data Setup Time

tDS

Data Hold Time

tDH

CS Setup Time

tCSS

CS High Pulse Width

tCSW

CLK Fall to CS Fall Hold Time

tCSH0

CLK Fall to CS Rise Hold Time

tCSH1

CS Rise to Clock Rise Setup

tCS1

See notes at end of section.

NOTES

1 Typical specifications represent average readings at 25°C and VDD = 5 V.

2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3 VAB = VDD, wiper (VW) = no connect.

4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6 Guaranteed by design and not subject to production test.

7PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

8All dynamic characteristics use VDD = 5 V.

9See timing diagrams for locations of measured values.

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