AS6C8008-55ZIN datasheet(4/11 Pages) ALSC

4 / 11 page

Notes:

1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.

2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.

3. Over/Undershoot specifications are characterized, not 100% tested.

4. Typical values are included for reference only and are not guaranteed or tested.

Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃

CAPACITANCE (TA = 25 , f = 1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX

UNIT

Input Capacitance

CIN

Input/Output Capacitance

CI/O

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0.2V to VCC - 0.2V

Input Rise and Fall Times

3ns

Input and Output Timing Reference Levels

1.5V

Output Load

CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

AS6C8008

PARAMETER

SYM.

UNIT

Read Cycle Time

tRC

Address Access Time

tAA

Chip Enable Access Time

tACE

Output Enable Access Time

tOE

Chip Enable to Output in Low-Z

tCLZ

Output Enable to Output in Low-Z

tOLZ

Chip Disable to Output in High-Z

tCHZ

Output Disable to Output in High-Z

tOHZ

Output Hold from Address Change

tOH

(2) WRITE CYCLE

AS6C8008

UNIT

PARAMETER

Write Cycle Time

tWC

Address Valid to End of Write

tAW

Chip Enable to End of Write

tCW

Address Set-up Time

tAS

Write Pulse Width

tWP

Write Recovery Time

tWR

Data to Write Time Overlap

tDW

Data Hold from End of Write Time

tDH

Output Active from End of Write

tOW

Write to Output in High-Z

tWHZ

*These parameters are guaranteed by device characterization, but not production tested.

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

JANUARY 2008

JANUARY/2008, V 1.0

Alliance Memory Inc.

Page 4 of 11

AS6C8008

1024K X 8 BIT SUPER LOW POWER CMOS SRAM

AS6C8008-55ZIN Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation

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