PC87364-XXXSLASHVLA datasheet(56/180 Pages) NSC

56 / 180 page

2.0 Device Architecture and Configuration (Continued)

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2.10.3

FDC Configuration Register

This register is reset by hardware to 24h.

Location:

Index F0h

Type:

R/W

Bit

76543210

Name

Reserved

TDR

Mode

DENSEL

Polarity

Control

Reserved

Write

Protect

PC-AT or

PS/2 Drive

Mode Select

Reserved

TRI-STATE

Control

Reset

00100100

Required

Bit

Description

Reserved. Must be 0.

TDR Register Mode

0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are 111111b (default)

1: Enhanced drive mode

DENSEL Polarity Control

0: Active low for 500 Kbps or 1 Mbps data rates

1: Active high for 500 Kbps or 1 Mbps data rates (default)

Reserved. Must be 0.

Write Protect. This bit allows forcing of write protect functionality by software. When set, writes to the floppy

disk drive are disabled. This effect is identical to WP when it is active.

0: Write protected according to WP signal (default)

1: Write protected regardless of value of WP signal

PC-AT or PS/2 Drive Mode Select

0: PS/2 drive mode

1: PC-AT drive mode (default)

Reserved

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

PC87364-XXX/VLA Datasheet(PDF) 56 Page - National Semiconductor (TI)

PC87364-XXX/VLA Datasheet(HTML) 56 Page - National Semiconductor (TI)

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