PC87364-XXXSLASHVLA datasheet(169/180 Pages) NSC

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10.0 Device Characteristics (Continued)

167

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10.2.7

Output, PCI 3.3V

Symbol: OPCI

10.2.8

Output, Totem-Pole Buffer

Symbol: Op/n

Output, Totem-Pole buffer that is capable of sourcing

p mA and sinking n mA

10.2.9

Output, Open-Drain Buffer

Symbol: ODn

Output, Open-Drain output buffer, capable of sinking

n mA. Output from these signals is open-drain and cannot be forced high.

10.2.10 Exceptions

1. All pins are back-drive protected, except for the output pins with PCI Buffer Type.

2. The following pins have a static pull-up resistor and therefore may have input leakage current (when VIN =VSS) of about

(-)160

µA: ACK, AFD_DSTRB, ERR, GPIO40-37, GPIO30-34,GPIO36-37, GPIO20-27, GPIO10-17, , GPIO00-07, INIT,

P12, P16, P17, PE, SLIN_ASTRB, STB_WRITE

3. The following pins have a static pull-down resistor and therefore may have input leakage current (when VIN =VDD)of

about 130

µA: BUSY_WAIT, PE, SLCT

4. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 Register is “0”) is open-drain in all SPP modes, except in

SPP Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1.

Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used.

5. Output from ACK, ERR (and PE if bit 2 of PP Confg0 Register is set to 1) is open-drain in all SPP modes, except in SPP

Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1.

Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used.

6. Output from STB, AFD, INIT, SLIN is open-drain in all SPP modes, except in SPP Compatible mode when the setup

mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 K

Ω pull-up resistors should be

used.

7. Output from PD7-0 is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based

(FIFO) and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is Level 2. External 4.7

Ω pull-up resistors should be used.

8. IOH is valid for a GPIO pin only when it is not configured as open-drain.

9. P12, P16 and P17 are driven high for about 100 ns after a low-to-high transition, during which it is capable of sourcing

2 mA.

Symbol

Parameter

Conditions

Min

Max

Unit

VOH

Output High Voltage

lout = -500 µA

0.9VDD

VOL

Output Low Voltage

lout =1500 µA

0.1 VDD

Symbol

Parameter

Conditions

Min

Max

Unit

VOH

Output High Voltage

IOH = −p mA

2.4

VOL

Output Low Voltage

IOL = n mA

0.4

Symbol

Parameter

Conditions

Min

Max

Unit

VOL

Output Low Voltage

IOL = n mA

0.4

PC87364-XXX/VLA Datasheet(PDF) 169 Page - National Semiconductor (TI)

PC87364-XXX/VLA Datasheet(HTML) 169 Page - National Semiconductor (TI)

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