TNETV2665ZWT4 datasheet(75/249 Pages) TI1

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TMS320C6424

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SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

•

PLL Output Frequency: (PLLOUT = CLKIN frequency * boot PLL Multiplier) must stay within the

PLLOUT frequency range in Table 6-15, PLLC1 Clock Frequency Ranges.

•

Device Frequency: (SYSCLK1) calculated from Table 3-5 must not exceed the SYSCLK1 maximum

frequency in Table 6-15, PLLC1 Clock Frequency Ranges.

For example, for a 600-MHz device with a CLKIN = 25 MHz, in order to stay within the PLLOUT

frequency range and SYSCLK1 maximum frequency from Table 6-15, PLLC1 Clock Frequency

Ranges, the user must select a boot mode with a PLL1 multiplier between x16 and x24.

3.4.1.3

EMIFA Boot Modes

As shown in Table 3-4 and Table 3-5, there are different types of EMIFA Boot Modes. This subsection

summarizes these types of EMIFA boot modes. For further detailed information, see the Using the

TMS320C642x Bootloader Application Report (literature number SPRAAK5).

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EMIFA ROM Direct Boot in PLL Bypass Mode (FASTBOOT = 0, BOOTMODE[3:0] = 0100b)

–

The C64x+ fetches the code directly from EMIFA Chip Select 2 Space [EM_CS2] (address

0x4200 0000)

–

The PLL is in Bypass Mode

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EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable

Asynchronous EMIF pins are available through configuration pins AEM[2:0]. AEM[2:0] must be

configured to 010b [EMIFA (Async) Pinout Mode 2].

•

EMIFA ROM Fastboot with AIS (FASTBOOT = 1, BOOTMODE[3:0] = 0100b)

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The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.

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The bootloader code programs PLLC1 to PLL Mode to speed up the boot process. The PLL

multiplier value is determined by the PLLMS[2:0] configuration as shown in Table 3-5.

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The bootloader code reads code from the EMIFA EM_CS2 space using the application image script

(AIS) format.

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EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable

Asynchronous EMIF pins are available through configuration pins AEM[2:0]. AEM[2:0] must be

configured to 010b [EMIFA (Async) Pinout Mode 2].

•

EMIFA ROM Fastboot without AIS: (FASTBOOT = 1, BOOTMODE[3:0] = 1001b)

–

The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.

–

The bootloader code programs PLLC1 to PLL Mode to speed up the boot process. The PLL

multiplier value is determined by the PLLMS[2:0] configuration as shown in Table 3-5.

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The bootloader code then jumps to the EMIFA EM_CS2 space, at which point the C64x+ fetches

the code directly from address 0x4200 0000.

–

EMIFA is configured as Asynchronous EMIF. The user is responsible for ensuring the desirable

Asynchronous EMIF pins are available through configuration pins AEM[2:0]. AEM[2:0] must be

configured to 010b [EMIFA (Async) Pinout Mode 2].

•

NAND Flash Boot: (FASTBOOT = 0 or 1, BOOTMODE[3:0] = 0111b)

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The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.

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Depending on the FASTBOOT and PLLMS[2:0] settings, the bootloader code may program the

PLLC1 to PLL Mode to speed up the boot process. See Table 3-4 and Table 3-5.

–

The bootloader code reads the code from EMIFA (NAND) EM_CS2 (address 0x4200 0000) using

AIS format.

–

EMIFA is configured in NAND mode. The user is responsible for ensuring the desirable

Asynchronous EMIF pins are available through configuration pins AEM[2:0]. AEM[2:0] can be

configured to 010b [EMIFA (Async) Pinout Mode 2] or 101b [EMIFA (NAND) Pinout Mode 5].

3.4.1.4

Serial Boot Modes (I2C, UART[UART0], SPI[McBSP0])

This subsection discusses how the bootloader configures the clock dividers for the serial boot modes—I2C

boot, UART boot, and SPI boot.

Device Configurations

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