PCM16C010 datasheet(13/38 Pages) NSC

13 / 38 page

50 Functional Description (Continued)

PCM16C010 shall not assert the STSCHG

signal If the

PCM16C010 is not operated as an IO interface this field is

undefined and should be ignored

IOis8

When the host can only provide IO cycles with an

8-bit D0 – D7 path the host shall set this bit to a one (1) The

card is guaranteed that accesses to 16-bit registers will oc-

cur as two byte accesses rather than a single 16-bit access

This information is useful when 16-bit and 8-bit registers

overlap

Audio

Sampling of the signal SPK

IN and control of

SPKR

is accomplished using the Audio bit SPKR

will

equate to SPK

IN anytime either of the Audio bits is set to

one (1) and the function is configured

PwrDn

When the host sets this field to one (1) the

PCM16C010 shall set the given function to a power-down

state by de-asserting the PCNTL signal for that function

While this field is a one (1) the host shall not access the

function on the PC Card The host shall return this field to

zero (0) before attempting to access the function The sys-

tem shall not place the card into a power-down state while

the card’s RDYBSY

line is in the low (Busy) state All

inputoutput

signals

particular

the

function

are

TRI-STATE

Intr

If the function is requesting interrupt servicing (CINT

asserted) the PCM16C010 shall set this field to one (1)

The PCM16C010 shall reset this field to zero (0) when the

interrupt request has been serviced (CINT de-asserted)

IntrReset

If IntrReset is set to zero (0) Intr shall be set to

one (1) when an interrupt condition occurs and shall be re-

set to zero (0) when the interrupt condition has been serv-

iced A write to the Intr bit will do nothing If IntrReset is set

to one (1) Intr shall be set to one (1) when an interrupt

condition occurs (CINT pin) and be cleared to a zero (0)

when the interrupt (CINT pin) is serviced however a write

of value zero (0) to the FCSR’s Intr bit where IntrReset is set

to one (1) shall cause the PCM16C010 to evaluate the CINT

signal and generate another interrupt to the system if an

interrupt is pending Note that the write of zero (0) to

FCSR’s Intr bit where IntrReset is set to one (1) is an indica-

tion to the PCM16C010 that it must evaluate CINT and gen-

erate a specified pulse to the system on the IREQ line This

protocol will work in either pulse or level mode (state of

aliased LevIREQ controlling IREQ

PC Card signal mode)

Functions operate by asserting their CINT signal when an

interrupt condition occurs If interrupts are enabled for a giv-

en function then that function’s CINT pin when asserted

may generate an interrupt within the PCM16C010

If other interrupts are pending the internal line remains as-

serted (and hence IREQ ) Since the standard PC compati-

ble interrupt controller requires a positive edge to trigger an

interrupt system software based on using the IntrReset pro-

tocol for the PCM16C010 may write a zero (0) to the Intr bit

where IntrReset is set to one (1) after EOI processing is

done This will cause the PCM16C010 to generate a pulse

on the IREQ

line if CINT is still asserted In other words if

the internal line is still asserted at this point If in pulse

mode this is a single pulse that goes high-low-high with at

least 05 ms low time If in level mode this pulse is a low-

high-low pulse to trigger the interrupt controller and then

remain low (IREQ

asserted) and be maintained low by the

level mode interrupt This protocol solves both the need for

two positive edges during level mode interrupts when an

interrupt occurs during an interrupt in-service and solves the

need for separate-distinct pulse interrupts that do not over-

lap during two interrupt events close in time

Function Pin Replacement Register

0x1024

This PC Card register replaces the signals missing from a

PC Card Memory Card interface due to using the PC Card

IO interface

CBVD1 CBVD2 CRdyBsy CWProt RBVD1 RBVD2 RRdyBsy RWProt

CBVD1CBVD2

These bits are not implemented

CRdyBsy

This bit is set to one (1) when RRdyBsy bit

changes state The value of 02h must be written to the Pin

Replacement Registers in order to clear the CRdyBsy bit

CWProt

This bit is not implemented

RBVD1RBVD2RRdyBsyRWProt

Only

RRdyBsy

implemented This bit reflects the state of the function’s

READY input pin on the PCM16C010

Function IO Event Register

0x1028

D7–D5

D3–D1

Reserved

RIEvt

Reserved

RIENAB

RIEvt

PCM16C010 latches a one (1) to the Card IO

Event Register’s RIEvt bit when RI

pin is asserted

provided the RIEnab bit is set The value of 10h must be

written to the IO Event Register in order to clear the RIEvt

bit (D4)

RIEnab

When this bit is set to a one (1) a latched value of

one (1) on the RIEvt bit shall cause the Changed bit in the

Function’s Configuration Status Register to be set to a one

(1)

Function Base Address Register

0x102A-0x102C

The base address for the function is comprised of 4 bytes

(13 bits implemented) that specify the base IO address

from which to begin decoding for chip selection of a particu-

lar function

Base A Register

D7–D0

Byte 0 (Base Address bits 7–0) of 13-bit Address

This register comprises the low 8 bits of the base address

for the Function IO decode selection

http

www nationalcom

PCM16C010 Datasheet(PDF) 13 Page - National Semiconductor (TI)

PCM16C010 Datasheet(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL