TNETV2685FIBZUT5 datasheet(108/191 Pages) TI1

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DM648

Device

DDR2Device

VREFNominalMinimum

TraceWidthis20Mils

VREFBypassCapacitor

NeckdowntominimuminBGA escaperegions

isacceptable.Narrowingtoaccommodatevia

congestionforshortdistancesisalsoacceptable.

Bestperformanceisobtainedifthewidthof

VREFismaximized.

DM648

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

www.ti.com

6.9.3.10 VREF Routing

VREF is used as a reference by the input buffers of the DDR2 memories as well as the device’s. VREF is

intended to be 1/2 the DDR2 power supply voltage and should be created using a resistive divider as

shown in Figure 6-11. Other methods of creating VREF are not recommended. Figure 6-15 shows the

layout guidelines for VREF.

DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:

DM647/DM648.

Figure 6-15. VREF Routing and Topology

6.9.3.11 DDR2 CK and ADDR_CTRL Routing

Figure 6-16 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a

balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A

should be maximized.

DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:

DM647/DM648.

Figure 6-16. CK and ADDR_CTRL Routing and Topology

108

Peripheral Information and Electrical Specifications

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Product Folder Link(s): TMS320DM647 TMS320DM648

TNETV2685FIBZUT5 Datasheet(PDF) 108 Page - Texas Instruments