ENICSF2811PBKA datasheet(81/172 Pages) TI1

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TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

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SPRS174T – APRIL 2001 – REVISED MAY 2012

The SPI port operation is configured and controlled by the registers listed in Table 4-10.

Table 4-10. SPI Registers(1)

NAME

ADDRESS

SIZE (x16)

DESCRIPTION

SPICCR

0x00 7040

SPI Configuration Control Register

SPICTL

0x00 7041

SPI Operation Control Register

SPISTS

0x00 7042

SPI Status Register

SPIBRR

0x00 7044

SPI Baud Rate Register

SPIRXEMU

0x00 7046

SPI Receive Emulation Buffer Register

SPIRXBUF

0x00 7047

SPI Serial Input Buffer Register

SPITXBUF

0x00 7048

SPI Serial Output Buffer Register

SPIDAT

0x00 7049

SPI Serial Data Register

SPIFFTX

0x00 704A

SPI FIFO Transmit Register

SPIFFRX

0x00 704B

SPI FIFO Receive Register

SPIFFCT

0x00 704C

SPI FIFO Control Register

SPIPRI

0x00 704F

SPI Priority Control Register

(1)

These registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.

Peripherals

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