TM8050H-8D3 datasheet(5/9 Pages) STMICROELECTRONICS

5 / 9 page

TM8050H-8D3

Characteristics

DocID028948 Rev 3

5/9

Figure 7: Surge peak on-state current versus

number of cycles

Figure 8: Non repetitive surge peak on-state

current for a half cycle sine pulse versus pulse

width (tp < 10 ms)

Figure 9: Relative variation of holding current and

latching current versus junction temperature

(typical values)

Figure 10: Relative variation of gate trigger current

and gate voltage versus junction temperature

Figure 11: Relative variation of leakage current

versus junction temperature for different values of

blocking voltage

Figure 12: Relative variation of static dV/dt

immunity versus junction temperature

(typical values)

100

150

200

250

300

350

400

450

500

550

600

650

700

750

100

1000

Number of cycles

ITSM(A)

Non repetitive

Tj initial = 25 °C

Repetitive

Tc = 130 °C

100

1000

10000

0.01

0.10

1.00

10.00

ITSM(A)

dI/dt limitation: 200 A/µs

ITSM

j initial = 25 °C

tP(ms)

0.0

0.3

0.5

0.8

1.0

1.3

1.5

1.8

2.0

-50

-25

100

125

150

Tj(°C)

IH, IL [Tj] / IH, IL [Tj = 25 °C]

0.0

0.5

1.0

1.5

2.0

-50

-25

100

125

150

Tj(°C)

IGT

VGT

IGT, VGT [Tj] / IGT, VGT [Tj = 25 °C]

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

1.0E+00

100

125

150

DRM= VRRM= 800 V

(typical values)

DRM = VRRM= 600 V

(typical values)

DRM= VRRM = 800 V

(maximum values)

Tj(°C)

IDRM, IRRM [Tj, VDRM, VRRM] / IDRM, IRRM [150 °C, 800 V]

110

130

150

VD= 0.67 x VDRM

Tj(°C)

dV/dt [Tj] / dV/dt [Tj = 150 °C]

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