ST72321R7-Auto datasheet(66/243 Pages) STMICROELECTRONICS

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Power saving modes

ST72321xx-Auto

66/243

Doc ID 13829 Rev 1

Figure 25.

Active Halt timing overview

This delay occurs only if the MCU exits Active Halt mode by means of a RESET.

Figure 26.

Active Halt mode flowchart

Peripheral clocked with an external clock source can still be active.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and restored when the CC register is

popped.

In Flash devices only the MCC/RTC interrupt can exit the MCU from Active Halt mode.

HALT

RUN

256 OR 4096 CPU

CYCLE DELAY(1)

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[MCCSR.OIE = 1]

HALT INSTRUCTION

RESET

CPU

OSCILLATOR

PERIPHERALS(1)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX(2)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX(2)

256 OR 4096 CPU CLOCK

CYCLE DELAY

(MCCSR.OIE = 1)

INTERRUPT (3)

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