ST72321R7-Auto datasheet(116/243 Pages) STMICROELECTRONICS

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16-bit timer

ST72321xx-Auto

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Doc ID 13829 Rev 1

13.7.4

Input capture 1 high register (IC1HR)

This is an 8-bit read only register that contains the high part of the counter value (transferred

by the input capture 1 event).

Table 62.

CSR register description

Bit

Name

Function

7ICF1

Input Capture Flag 1

0: No input capture (reset value)

1: An input capture has occurred on the ICAP1 pin or the counter has reached the

OC2R value in PWM mode. To clear this bit, first read the SR register, then read

or write the low byte of the IC1R (IC1LR) register.

6OCF1

Output Compare Flag 1

0: No match (reset value)

1: The content of the free running counter has matched the content of the OC1R

of the OC1R (OC1LR) register.

5TOF

Timer Overflow Flag

0: No timer overflow (reset value)

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first

read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

4ICF2

Input Capture Flag 2

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the

SR register, then read or write the low byte of the IC2R (IC2LR) register.

3OCF2

Output Compare Flag 2

0: No match (reset value)

1: The content of the free running counter has matched the content of the OC2R

of the OC2R (OC2LR) register.

2TIMD

Timer disable

This bit is set and cleared by software. When set, it freezes the timer prescaler

and counter and disabled the output functions (OCMP1 and OCMP2 pins) to

reduce power consumption. Access to the timer registers is still available, allowing

the timer configuration to be changed, or the counter reset, while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

1:0

Reserved, must be kept cleared

IC1HR

Reset value: Undefined

543

MSB

LSB

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