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ST72325AR7-Auto Datasheet(PDF) 61 Page - STMicroelectronics |
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ST72325AR7-Auto Datasheet(HTML) 61 Page - STMicroelectronics |
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61 / 243 page  Obsolete Product(s) - Obsolete Product(s) ST72325xxx-Auto Interrupts Doc ID 13770 Rev 3 61/243 7.6 External interrupts 7.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 23). This control allows to have up to four fully independent external interrupt source sensitivities. Table 21. Interrupt mapping No. Source block Description Register label Priority order Exit from Halt / Active Halt Address vector RESET Reset N/A yes FFFEh-FFFFh TRAP Software interrupt no FFFCh-FFFDh 0 TLI External top level interrupt EICR yes FFFAh-FFFBh 1 MCC/RTC CSS Main clock controller time base interrupt Safe oscillator activation interrupt MCCSRSI CSR Higher priority yes FFF8h-FFF9h 2 ei0 External interrupt port A3..0 N/A yes FFF6h-FFF7h 3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h 4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h 5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h 6 Not used FFEEh-FFEFh 7 SPI SPI peripheral interrupts SPICSR yes(1) FFECh-FFEDh 8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh 9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h 10 SCI SCI peripheral interrupts SCISR Lower priority no FFE6h-FFE7h 11 AVD Auxiliary voltage detector interrupt SICSR no FFE4h-FFE5h 12 I2C I2C peripheral interrupts (see peripheral) no FFE2h-FFE3h 13 PWM ART PWM ART interrupt ARTCSR yes(2) FFE0h-FFE1h 1. Exit from HALT possible when SPI is in slave mode. 2. Exit from HALT possible when PWM ART is in external clock mode. |
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