ST72325AR7-Auto datasheet(201/243 Pages) STMICROELECTRONICS

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ST72325xxx-Auto

Electrical characteristics

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19.5.6

PLL characteristics

The user must take the PLL jitter into account in the application (for example, in serial

communication or sampling of high frequency signals). The PLL jitter is a periodic effect,

which is integrated over several CPU cycles. Therefore, the longer the period of the

application signal, the less it is impacted by the PLL jitter.

Figure 79 shows the PLL jitter integrated on application signals in the range 125 kHz to

4 MHz. At frequencies of less than 125 kHz, the jitter is negligible.

Figure 79.

Integrated PLL jitter versus signal frequency(1)

Measurement conditions: fCPU = 8 MHz

19.6

Memory characteristics

19.6.1

RAM and hardware registers

Table 121.

PLL characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fOSC

PLL input frequency range

MHz

 f

CPU/fCPU

Instantaneous PLL jitter(1)

Data characterized but not tested

fOSC = 4 MHz

0.7

0.2

0.4

0.6

0.8

1.2

4 MHz

2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

Application Frequency

+/-Jitter (%)

Max

Typ

Table 122.

RAM supply voltage

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VRM

Data retention mode(1)

Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in

hardware registers (only in Halt mode). Not tested in production.

Halt mode (or RESET)

1.6

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