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STM8L101x2 Datasheet(PDF) 54 Page - STMicroelectronics |
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STM8L101x2 Datasheet(HTML) 54 Page - STMicroelectronics |
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54 / 88 page  Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3 54/88 DocID15275 Rev 16 Figure 31. Typical NRST pull-up current Ipu vs. VDD The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 30. Otherwise the reset is not taken into account internally. For power consumption- sensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. The minimum recommended capacity is 10 nF. Figure 32. Recommended NRST pin configuration 1. Correct device reset during power on sequence is guaranteed when tVDD[max] is respected. 2. External reset circuit is recommended to ensure correct device reset during power down, when VPDR < VDD < VDD[min]. |
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