AS4C64M8D1 datasheet(2/64 Pages) ALSC

2 / 64 page

AS4C64M8D1

Confidential

Rev.

2.0

Oct. /2014

512M – (64M x 8 bit) DDR Synchronous DRAM (SDRAM)

Confidential

(Rev. 2.0, Oct. /2014)

Features

 Fast clock rate: 200MHz

 Differential Clock CK & CK

 Bi-directional DQS

 DLL enable/disable by EMRS

 Fully synchronous operation

 Internal pipeline architecture

 Four internal banks, 16M x 8-bit for each bank

 Programmable Mode and Extended Mode registers

- CAS Latency: 2, 2.5, 3

- Burst length: 2, 4, 8

- Burst Type: Sequential & Interleaved

 Individual byte write mask control

 DM Write Latency = 0

 Auto Refresh and Self Refresh

 8192 refresh cycles / 64ms

 Precharge & active power down

 Operating temperature range: TA = 0 ~ 70°C

 Power supplies: VDD & VDDQ = 2.5V ± 0.2V

 Interface: SSTL_2 I/O Interface

 Package: 66 Pin TSOP II, 0.65mm pin pitch

 Package: 60-Ball, 8x13x1.2 mm (max) TFBGA

- All parts ROHS Compliant

Overview

The 512Mb DDR SDRAM is a high-speed CMOS

double data rate synchronous DRAM containing 512

Mbits. It is internally configured as a quad 16M x 8-bit

DRAM with a synchronous interface (all signals are

registered on the positive edge of the clock signal, CK).

Data outputs occur at both rising edges of CK and CK .

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence. Accesses begin with the

registration of a BankActivate command which is then

followed by a Read or Write command. The

DDR

SDRAM provides programmable Read or Write burst

lengths of 2, 4, or 8. An auto precharge function may

be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence. The

refresh functions, either Auto or Self Refresh are easy

to use. In addition,

The DDR SDRAM features

programmable DLL option. By having a programmable

mode register and extended mode register, the system

can choose the most suitable modes to maximize its

performance. These devices are well suited for

applications requiring high memory bandwidth, result in

a device particularly well suited to high performance

main memory and graphics applications.

Table 1. Ordering Information

Part Number

Clock Frequency

Data Rate

Power Supply

Package

AS4C64M8D1-5TCN

200MHz

400Mbps/pin

VDD 2.5V, VDDQ 1.8V

66pin TSOP II

AS4C64M8D1-5TIN

200MHz

400Mbps/pin

VDD 2.5V, VDDQ 1.8V

66 pin TSOP II

AS4C64M8D1-5BCN

200MHz

400Mbps/pin

VDD 2.5V, VDDQ 1.8V

60 ball TFBGA

AS4C64M8D1-5BIN

200MHz

400Mbps/pin

VDD 2.5V, VDDQ 1.8V

60 ball TFBGA

T: indicated 66 pin TSOP II B: indicates 60-ball 8 x 10 x 1.2mm (max) TFBGA package

C: indicates commercial temperature

I: indicates industrial temperature

N: indicates Pb and Halogen Free - ROHS Compliant

Table 2. Speed Grade Information

Speed Grade

Clock Frequency

CAS Latency

tRCD (ns)

tRP (ns)

DDR1-400

200 MHz

2.5

AS4C64M8D1 Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation

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