AS4C64M8D2 datasheet(15/59 Pages) ALSC

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AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

Table 10. Burst Definition, Addressing Sequence of Sequential and Interleave Mode

Burst Length

Start Address

Sequential

Interleave

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

7, 6, 5, 4, 3, 2, 1, 0

 Burst read command

The Burst Read command is initiated by having CS# and CAS# LOW while holding RAS# and WE# HIGH at the

rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from

the start of the command to when the data from the first cell appears on the outputs is equal to the value of the

Read Latency (RL). The data strobe output (DQS) is driven LOW 1 clock cycle before valid data (DQ) is driven

onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each

subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The

RL is equal to an additive latency (AL) plus CAS Latency (CL). The CL is defined by the Mode Register Set

(MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register Set (1)

(EMRS (1)).

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the

setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design.

The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode,

timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential

mode, these timing relationships are measured relative to the cross point of DQS and its complement, DQS#.

This distinction in timing methods is guaranteed by design and characterization. Note that when differential data

strobe mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to VSS through a

20 Ω to 10 KΩ resistor to insure proper operation.

 Burst write operation

The Burst Write command is initiated by having CS#, CAS# and WE# LOW while holding RAS# HIGH at the

rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined

by a Read latency (RL) minus one and is equal to (AL + CL -1);and is the number of clocks of delay that are

required from the time the Write command is registered to the clock edge associated to the first DQS strobe. A

data strobe signal (DQS) should be driven LOW (preamble) one clock prior to the WL. The first data bit of the

burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS

specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles.

The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed,

which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored.

The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst

Write to bank precharge is the write recovery time (WR). DDR2 SDRAM pin timings are specified for either single

ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing

advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin

timings are measured is mode dependent.

In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at

the specified AC/DC levels. In differential mode, these timing relationships are measured relative to the cross

point of DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and

characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin,

DQS#, must be tied externally to VSS through a 20Ω to 10KΩ resistor to insure proper operation.

AS4C64M8D2 Datasheet(PDF) 15 Page - Alliance Semiconductor Corporation

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