AS8C803601 datasheet(16/21 Pages) ALSC

Part #	AS8C803601

Description	Three chip enables for simple depth expansion

PDF	21 Pages

Scroll/Zoom	100%

Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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16 / 21 page

tHE

tSE

CLK

CEN

ADV/

ADDRESS

CE1, CE2(2)

BW1 - BW4

DATAOUT

Q(A3)

Q(A1)

Q(A6)

Q(A7)

tCD

Read

tCHZ

5304 drw 08

Write

tCLZ

D(A2)

D(A4)

tCDC

D(A5)

Write

tCH

tCL

tCYC

tHW

tSW

tHA

tSA

tHC

tSC

tSD tHD

tHADV

tSADV

DATAIN

tHB

tSB

Read

NOTES:

1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.

2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.

3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two

cycles before the actual data is presented to the SRAM.

AS8C803601 Datasheet(PDF) 16 Page - Alliance Semiconductor Corporation

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