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AS8C803625 Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS8C803625 Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 22 page  NOVEMBER 2010 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect AS8C803625 AS8C801825 Features 256K x 36, 512K x 18 memory configuration Supports fast access times: - 7.5ns up to 117MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP) to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the 803625/801825 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The orders of these three addresses are defined by the internal burst counter and the LBO input pin. The 803625/801825 SRAMs utilize Alliance’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP). Description The 803625/801825 are high-speed SRAMs organized as 256K x 36/512K x 18. The 803625/801825 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow- through architecture). Internal logic allows the SRAM Pin Description Summary A0 – A18 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4 (1) Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous ADSP Address Status (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0 – I/O31, I/OP1 – I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A NOTE: 5309 tbl 01 1. BW3 and BW4 are not applicable for 803625/801825. |
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