M68AW128ML55ZB1F datasheet(8/22 Pages) STMICROELECTRONICS

8 / 22 page

M68AW128M

8/22

OPERATION

The M68AW128M has a Chip Enable power down

feature which invokes an automatic standby mode

whenever either Chip Enable is de-asserted

(E = High) or LB and UB are de-asserted (LB and

UB = High). An Output Enable (G) signal provides

a high speed tri-state control, allowing fast read/

write cycles to be achieved with the common I/O

data bus. Operational modes are determined by

device control inputs W, E, LB and UB as summa-

rized in the Operating Modes table (see Table 2).

Read Mode

The M68AW128M is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, and Chip Enable (E) is asserted. This pro-

vides access to data from eight or sixteen, de-

pending on the status of the signal UB and LB, of

the 2,097,152 locations in the static memory array,

specified by the 17 address inputs. Valid data will

be available at the eight or sixteen output pins

within tAVQV after the last stable address, provid-

ing G is Low and E is Low. If Chip Enable or Output

Enable access times are not met, data access will

be measured from the limiting parameter (tELQV,

tGLQV or tBLQV) rather than the address. Data out

may be indeterminate at tELQX, tGLQX and tBLQX

but data lines will always be valid at tAVQV.

Write Mode

The M68AW128M is in the Write mode whenever

the W and E are Low. Either the Chip Enable input

(E) or the Write Enable input (W) must be de-

asserted

during

Address

transitions

for

subsequent write cycles. When E (W) is Low, and

UB or LB is Low, write cycle begins on the W (E)'s

falling edge. When E and W are Low, and UB = LB

= High, write cycle begins on the first falling edge

of UB or LB. Therefore, address setup time is

referenced to Write Enable, Chip Enable or UB/LB

as tAVWL, tAVEL and tAVBL respectively, and is

determined by the latter occurring edge.

The Write cycle can be terminated by the earlier

rising edge of E, W or UB/LB.

If the Output is enabled (E = Low, G = Low, LB or

UB = Low), then W will return the outputs to high

impedance within tWLQZ of its falling edge. Care

must be taken to avoid bus contention in this type

of operation. Data input must be valid for tDVWH

before the rising edge of Write Enable, or for tDVEH

before the rising edge of E, or for tDVBH before the

Table 2. Operating Modes

Note: 1. X = VIH or VIL.

Operation

DQ0-DQ7

DQ8-DQ15

Power

Deselected

VIH

XXXX

Hi-Z

Standby (ISB)

Deselected

VIH

Hi-Z

Standby (ISB)

Lower Byte Read

VIL

VIH

VIL

VIH

Data Output

Hi-Z

Active (ICC)

Lower Byte Write

VIL

VIH

Data Input

Hi-Z

Active (ICC)

Output Disabled

VIL

VIH

Hi-Z

Active (ICC)

Upper Byte Read

VIL

VIH

VIL

VIH

VIL

Hi-Z

Data Output

Active (ICC)

Upper Byte Write

VIL

VIH

VIL

Hi-Z

Data Input

Active (ICC)

Word Read

VIL

VIH

VIL

Data Output

Active (ICC)

Word Write

VIL

Data Input

Active (ICC)

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