WM8773

Product Preview

PP Rev 1.0 June 2002

18

CONTROL INTERFACE REGISTERS

DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the FMT[1:0] register bits:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10110

Interface Control

1:0

FMT[1:0]

10

Interface format Select

00 : right justified mode

01: left justified mode

10: I

11: DSP (early or late) mode

In left justified, right justified or I

this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown Figure 9, and.

Note that if this feature is used as a means of swapping the left and right channels, a 1 sample

phase difference will be introduced. In DSP modes, the LRP register bit is used to select between

early and late modes.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

In left/right/I

ADCLRC Polarity (normal)

0 : normal ADCLRC polarity

1: inverted ADCLRC polarity

10110

Interface Control

2

LRP

0

In DSP mode:

0 : Early DSP mode

1: Late DSP mode

By default, ADCLRC is sampled on the rising edge of BCLK and should ideally change on the falling

edge. Data sources that change ADCLRC on the rising edge of BCLK can be supported by setting

the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in

Figure 9, Figure 10, Figure 11, Figure 12, and Figure 13.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10110

Interface Control

3

BCP

0

BCLK Polarity (DSP modes)

0 : normal BCLK polarity

1: inverted BCLK polarity

The WL[1:0] bits are used to control the word length.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

10110

Interface Control

5:4

WL[1:0]

10

Word Length

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note:

1.

If 32-bit mode is selected in right justified mode, the WM8773 defaults to 24 bits.

2.

In 24 bit I

minimum of 24 BCLKs and low for a minimum of 24 BCLKs.