27

INA231

www.ti.com

SBOS644A – FEBRUARY 2013 – REVISED JUNE 2017

Product Folder Links: INA231

Submit Documentation Feedback

Copyright © 2013–2017, Texas Instruments Incorporated

POL:

Power Overlimit

Bit 11

Setting this bit high configures the ALERT pin to be asserted when the power calculation exceeds the value in the

Alert Limit register.

CNVR:

Conversion Ready

Bit 10

Setting this bit high configures the ALERT pin to be asserted when the Conversion Ready Flag bit (CVRF, bit 3) is

asserted, indicating that the device is ready for the next conversion.

AFF:

Alert Function Flag

Bit 4

Although only one alert function at a time can be monitored at the ALERT pin, the Conversion Ready bit (CNVR, bit

10) can also be enabled to assert the ALERT pin. Reading the Alert Function Flag bit after an alert can help

determine if the alert function was the source of the alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable

register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared

after the next conversion that does not result in an alert condition.

CVRF:

Conversion Ready Flag

Bit 3

Although the INA231 can be read at any time, and the data from the last conversion are available, this bit is

provided to help coordinate single-shot or triggered conversions. This bit is set after all conversions, averaging, and

multiplications are complete. This bit clears under the following conditions in single-shot mode:

1) Writing to the Configuration register (except for power-down or disable selections)

2.) Reading the Mask/Enable register

OVF:

Math Overflow Flag

Bit 2

This bit is set to 1 if an arithmetic operation results in an overflow error; it indicates that current and power data may

be invalid.

APOL:

Alert Polarity

Bit 1

Configures the latching feature of the ALERT pin and the flag bits.

1 = Inverted (active-high open collector)

0 = Normal (active-low open collector) (default)

LEN:

Alert Latch Enable

Bit 0

Configures the latching feature of the ALERT pin and flag bits.

1 = Latch enabled

0 = Transparent (default)

When the Alert Latch Enable bit is set to Transparent mode, the ALERT pin and flag bits reset to their idle states

when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the ALERT pin and flag bits

remain active following a fault until the Mask/Enable register has been read.

8.6.8 Alert Limit Register (07h, Read/Write)

The Alert Limit register contains the value used to compare to the register selected in the Mask/Enable register

to determine if a limit has been exceeded.

Table 15. Alert Limit Register (07h, Read/Write) Description

BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT

NAME

AUL15

AUL14

AUL13

AUL12

AUL11

AUL10

AUL9

AUL8

AUL7

AUL6

AUL5

AUL4

AUL3

AUL2

AUL1

AUL0

POR

VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0