R5F104FDA datasheet(94/213 Pages) RENESAS

94 / 213 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

°C)

R01DS0053EJ0330 Rev. 3.30

Page 94 of 208

Aug 12, 2016

Note 1.

Transfer rate in the SNOOZE mode is 4800 bps only.

However, the SNOOZE mode cannot be used when FRQSEL4 = 1.

Note 2.

Use it with EVDD0

≥ Vb.

Note 3.

The following conditions are required for low voltage interface when EVDD0 < VDD.

2.4 V

≤ EVDD0 < 2.7 V: MAX. 2.6 Mbps

1.8 V

≤ EVDD0 < 2.4 V: MAX. 1.3 Mbps

Note 4.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode:

32 MHz (2.7 V

≤ VDD ≤ 5.5 V)

16 MHz (2.4 V

≤ VDD ≤ 5.5 V)

LS (low-speed main) mode:

8 MHz (1.8 V

≤ VDD ≤ 5.5 V)

LV (low-voltage main) mode:

4 MHz (1.6 V

≤ VDD ≤ 5.5 V)

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin

products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the TxDq pin by using port input mode

input buffer selected.

Remark 1.

Vb [V]: Communication line voltage

Remark 2.

q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)

Remark 3.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00 to 03, 10 to 13)

Remark 4.

UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is

(6)

Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)

(TA = -40 to +85°C, 1.6 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

mode

LS (low-speed main)

mode

LV (low-voltage main)

mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Transfer

rate

reception

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

fMCK/6 Note 1

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK Note 4

5.3

1.3

0.6

Mbps

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V

fMCK/6 Note 1

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK Note 4

5.3

1.3

0.6

Mbps

1.8 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V

fMCK/6

Notes 1, 2, 3

fMCK/6

Notes 1, 2

fMCK/6

Notes 1, 2

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK Note 4

5.3

1.3

0.6

Mbps

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