R5F104FDA datasheet(155/213 Pages) RENESAS

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RL78/G14

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105

°C)

R01DS0053EJ0330 Rev. 3.30

Page 155 of 208

Aug 12, 2016

3.5

Peripheral Functions Characteristics

AC Timing Test Points

3.5.1

Serial array unit

Note 1.

Transfer rate in the SNOOZE mode is 4800 bps only.

However, the SNOOZE mode cannot be used when FRQSEL4 = 1.

Note 2.

The following conditions are required for low voltage interface when EVDD0

< VDD.

2.4 V

≤ EVDD0 < 2.7 V: MAX. 1.3 Mbps

Note 3.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode:

32 MHz (2.7 V

≤ VDD ≤ 5.5 V)

16 MHz (2.4 V

≤ VDD ≤ 5.5 V)

Caution

Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input

mode register g (PIMg) and port output mode register g (POMg).

UART mode connection diagram (during communication at same potential)

UART mode bit width (during communication at same potential) (reference)

Remark 1.

q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)

Remark 2.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00 to 03, 10 to 13))

(1)

During communication at same potential (UART mode)

(TA = -40 to +105°C, 2.4 V

≤ EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

Transfer rate Note 1

2.4 V

≤ EVDD0 ≤ 5.5 V

fMCK/12 Note 2

bps

Theoretical value of the maximum transfer rate

fMCK = fCLK Note 3

2.6

Mbps

VIH/VOH

VIL/VOL

VIH/VOH

Test points

VIL/VOL

RL78 microcontroller

TxDq

RxDq

User’s device

Baud rate error tolerance

TxDq

RxDq

High-/Low-bit width

1/Transfer rate

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