R5F104FDA datasheet(160/213 Pages) RENESAS

160 / 213 page

RL78/G14

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105

°C)

R01DS0053EJ0330 Rev. 3.30

Page 160 of 208

Aug 12, 2016

Note 1.

The value must also be equal to or less than fMCK/4.

Note 2.

Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.

Caution

Select the normal input buffer and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin

products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the normal output mode

for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).

(Remarks are listed on the next page.)

(4)

During communication at same potential (simplified I2C mode)

(TA = -40 to +105°C, 2.4 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) mode

Unit

MIN.

MAX.

SCLr clock frequency

fSCL

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

400 Note 1

kHz

2.4 V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

100 Note 1

kHz

Hold time when SCLr = “L”

tLOW

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

1200

2.4V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

4600

Hold time when SCLr = “H”

tHIGH

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

1200

2.4 V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

4600

Data setup time (reception)

tSU: DAT

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

1/fMCK + 220 Note 2

2.4V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1/fMCK + 580 Note 2

Data hold time (transmission)

tHD: DAT

2.7 V

≤ EVDD0 ≤ 5.5 V,

Cb = 50 pF, Rb = 2.7 k

770

2.4 V

≤ EVDD0 ≤ 5.5 V,

Cb = 100 pF, Rb = 3 k

1420

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