R5F104FDA datasheet(168/213 Pages) RENESAS

168 / 213 page

RL78/G14

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105

°C)

R01DS0053EJ0330 Rev. 3.30

Page 168 of 208

Aug 12, 2016

Note

When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin

products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port

input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics

with TTL input buffer selected.

(Remarks are listed on the next page.)

(6)

Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output)

(TA = -40 to +105°C, 2.4 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

(3/3)

Parameter

Symbol

Conditions

HS (high-speed main) mode

Unit

MIN.

MAX.

SIp setup time (to SCKp↓) Note

tSIK1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2.4 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

220

SIp hold time (from SCKp↓) Note

tKSI1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2.4 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

Delay time from SCKp↑ to SOp output Note

tKSO1

4.0 V

≤ EVDD0 ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2.7 V

≤ EVDD0 < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2.4 V

≤ EVDD0 < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

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